公开(公告)号：US10580787B2

公开(公告)日：2020-03-03

申请号：US15991268

申请日：2018-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi Nishikawa ,  Fumiaki Toyama

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/06 ,  H01L21/762

Abstract: At least one diode, lower-level metal interconnect structures embedded within lower-level dielectric material layers, and a doped semiconductor material layer are formed over a semiconductor substrate. An electrically conductive path is provided between the at least one diode and the doped semiconductor material layer. An alternating stack of insulating layers and spacer material layers and memory stack structures extending therethrough are formed above the doped semiconductor material layer. A backside trench is formed through the alternating stack. The electrically conductive path is employed during plasma etch processes employed to form the memory stack structures and the backside trench to provide a discharge path for accumulated electrical charges. The electrically conductive path is subsequently disconnected by removing a conductive component underlying the backside trench. The spacer material layers can be replaced with electrically conductive layers employing the backside trench.

公开(公告)号：US10354987B1

公开(公告)日：2019-07-16

申请号：US15928340

申请日：2018-03-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Akio Nishida ,  Kenji Sugiura ,  Hisakazu Otoi ,  Masatoshi Nishikawa

IPC: H01L25/00 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L25/18 ,  H01L27/11582 ,  H01L27/11556

Abstract: Sacrificial pillar structures are formed through a first semiconductor substrate on which first semiconductor devices are subsequently formed. After backside thinning of the first semiconductor substrate, the sacrificial pillar structures are replaced with integrated through-substrate via and pad structures to provide a first semiconductor chip. A second semiconductor chip is provided, which includes a second semiconductor substrate, second semiconductor devices, and second bonding pad structures electrically connected to a respective one of the second semiconductor devices. The first bonding pad structures are bonded to a respective one of the second bonding pad structures by surface activated bonding.

公开(公告)号：US10354980B1

公开(公告)日：2019-07-16

申请号：US15928407

申请日：2018-03-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Akio Nishida ,  Kenji Sugiura ,  Hisakazu Otoi ,  Masatoshi Nishikawa

IPC: H01L25/00 ,  H01L25/065 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/00 ,  H01L21/822

Abstract: Multiple semiconductor chips can be bonded through copper-to-copper bonding. The multiple semiconductor chips include a logic chip and multiple memory chips. The logic chip includes a peripheral circuitry for operation of memory devices within the multiple memory chips. The memory chips can include front side bonding pad structures, backside bonding pad structures, and sets of metal interconnect structures providing electrically conductive paths between pairs of a first side bonding pad structure and a backside bonding pad structure. Thus, electrical control signal can vertically propagate between the logic chip and an overlying memory chip through at least one intermediate memory chip located between them. The backside bonding pad structures can be formed as portions of integrated through-substrate via and pad structures that extend through a respective semiconductor substrate.