公开(公告)号：US06686632B2

公开(公告)日：2004-02-03

申请号：US09839966

申请日：2001-04-23

申请人： Seiki Ogura ,  Yutaka Hayashi ,  Tomoko Ogura

发明人： Seiki Ogura ,  Yutaka Hayashi ,  Tomoko Ogura

IPC分类号： H01L29792

CPC分类号： H01L27/11568 ,  G11C11/5671 ,  G11C16/0475 ,  H01L27/115

摘要： A fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is described. The structure and operation of this invention is enabled by a twin MONOS cell structure having an ultra-short control gate channel of less than 40 nm, with ballistic injection which provides high electron injection efficiency and very fast program at low program voltages of 3˜5V. The ballistic MONOS memory cell is arranged in the following array: each memory cell contains two nitride regions for one word gate, and ½ a source diffusion and ½ a bit diffusion. Control gates can be defined separately or shared together over the same diffusion. Diffusions are shared between cells and run in parallel to the side wall control gates, and perpendicular to the word line. The features of fast program, low voltage, ultra-high density, dual-bit, multi-level MONOS NVRAM of the present invention include: 1) Electron memory storage in nitride regions within an ONO layer underlying the control gates, 2) high density dual-bit cell in which there are two nitride memory storage elements per cell, 3) high density dual-bit cell can store multi-levels in each of the nitride regions, 4) low current program controlled by the word gate and control gate, 5) fast, low voltage program by ballistic injection utilizing the controllable ultra-short channel MONOS, and 6) side wall control poly gates to program and read multi-levels while masking out memory storage state effects of the unselected adjacent nitride regions and memory cells.

摘要翻译： 描述了一种快速低电压弹道程序，超短通道，超高密度双位多级闪存。 本发明的结构和操作通过具有小于40nm的超短控制栅极通道的双重MONOS单元结构实现，具有提供高电子注入效率的弹道注入和在3〜5V的低编程电压下非常快速的程序 。 弹道MONOS存储单元被布置在以下阵列中：每个存储单元包含用于一个字门的两个氮化物区域，以及1/2扩散源和1/2位扩散。 控制门可以单独定义，也可以通过相同的扩散共享。 扩散在单元之间共享并且平行于侧壁控制栅极并垂直于字线。 本发明的快速程序，低电压，超高密度，双位多级MONOS NVRAM的特征包括：1）在控制门下面的ONO层内的氮化物区域中的电子存储器存储，2）高密度 每个单元有两个氮化物存储器元件的双位单元，3）高密度双位单元可以在每个氮化物区域中存储多个电平; 4）由字门和控制栅极控制的低电流程序， 5）通过使用可控超短通道MONOS的弹道注射的快速，低电压程序，以及6）侧壁控制多门程序来编程和读取多级，同时掩蔽未选择的相邻氮化物区域和存储器单元的存储器存储状态效应 。

公开(公告)号：US06628546B2

公开(公告)日：2003-09-30

申请号：US10371836

申请日：2003-02-20

申请人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

发明人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

IPC分类号： G11C1604

CPC分类号： G11C16/3459 ,  G11C16/0475 ,  G11C16/12 ,  G11C16/3454

摘要： In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

公开(公告)号：US06459622B1

公开(公告)日：2002-10-01

申请号：US10099030

申请日：2002-03-15

申请人： Seiki Ogura ,  Tomoko Ogura

发明人： Seiki Ogura ,  Tomoko Ogura

IPC分类号： G11C1604

CPC分类号： G11C16/0475 ,  G11C16/10

摘要： The present invention provides a method of memory cell selection and operation to obtain wide program bandwidth and EEPROM erase capability. Two storage sites within a memory cell can be simultaneously selected during read, program and erase. By proper biasing, each of the sites can be independently read and programmed. Also, during program, the source of energy to produce the current flow can be dynamically obtained from the stored charge on the selected bit line. If the bit line capacitance is not adequate to provide a charge that is necessary, additional bit line capacitance is borrowed from unselected bit lines, or a source follower select transistor may be used.

摘要翻译： 本发明提供一种存储单元选择和操作的方法，以获得宽的程序带宽和EE​​PROM擦除能力。 可以在读取，编程和擦除期间同时选择存储单元内的两个存储位置。 通过适当的偏置，每个站点都可以独立读取和编程。 此外，在程序期间，可以从所选位线上的存储电荷动态地获得产生电流的能量源。 如果位线电容不足以提供必要的电荷，则附加位线电容从未选择的位线借来，或者可以使用源极跟随器选择晶体管。

公开(公告)号：US06248633B1

公开(公告)日：2001-06-19

申请号：US09426692

申请日：1999-10-25

申请人： Seiki Ogura ,  Yutaba Hayashi ,  Tomoko Ogura

发明人： Seiki Ogura ,  Yutaba Hayashi ,  Tomoko Ogura

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  G11C11/5671 ,  G11C16/0475 ,  H01L27/115

摘要： A fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is described with a two or three polysilicon split gate side wall process. The structure and operation of this invention is enabled by a twin MONOS cell structure having an ultra-short control gate channel of less than 40nm, with ballistic injection which provides high electron injection efficiency and very fast program at low program voltages of 3˜5V. The cell structure is realized by (i) placing side wall control gates over a composite of Oxide-Nitride-Oxide (ONO) on both sides of the word gate, and (ii) forming the control gates and bit diffusion by self-alignment and sharing the control gates and bit diffusions between memory cells for high density. Key elements used in this process are: 1) Disposable side wall process to fabricate the ultra short channel and the side wall control gate with or without a step structure, and 2) Self-aligned definition of the control gate over the storage nitride and the bit line diffusion, which also runs in the same direction as the control gate. The features of fast program, low voltage, ultra-high density, dual-bit, multi-level MONOS NVRAM of the present invention include: 1) Electron memory storage in nitride regions within an ONO layer underlying the control gates, 2) high density dual-bit cell in which there are two nitride memory storage elements per cell, 3) high density dual-bit cell can store multi-levels in each of the nitride regions, 4) low current program controlled by the word gate and control gate, 5) fast, low voltage program by ballistic injection utilizing the controllable ultra-short channel MONOS, and 6) side wall control poly gates to program and read multi-levels while masking out memory storage state effects of the unselected adjacent nitride regions and memory cells. The ballistic MONOS memory cell is arranged in the following array: each memory cell contains two nitride regions for one word gate, and ½ a source diffusion and ½ a bit diffusion. Control gates can be defined separately or shared together over the same diffusion. Diffusions are shared between cells and run in parallel to the side wall control gates, and perpendicular to the word line.

公开(公告)号：US06177318B1

公开(公告)日：2001-01-23

申请号：US09419561

申请日：1999-10-18

申请人： Seiki Ogura ,  Yutaka Hayashi ,  Tomoko Ogura

发明人： Seiki Ogura ,  Yutaka Hayashi ,  Tomoko Ogura

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L27/11521

摘要： A fabrication method for an electrically programmable read only memory device, which consists of a control/word gate and a MONOS control gate on the side wall of the control gate. The unique material selection and blocking mask sequences allow simple and safe fabrication within the delicate scaled CMOS process environment, of a sidewall MONOS control gate with an ultra short channel under the control gate, which involves double side wall spacer formation i.e., a disposable side wall spacer and the final polysilicon spacer gate.

摘要翻译： 一种用于电可编程只读存储器件的制造方法，其由控制/字门和控制栅极侧壁上的MONOS控制栅极组成。 独特的材料选择和阻挡掩模序列允许在精细缩放的CMOS工艺环境内简单和安全地制造具有在控制栅极下方的超短通道的侧壁MONOS控制栅极，其涉及双侧壁间隔物形成，即一次性侧壁 间隔物和最终的多晶硅间隔栅极。

公开(公告)号：US20130094299A1

公开(公告)日：2013-04-18

申请号：US13692503

申请日：2012-12-03

申请人： Nori Ogura ,  Tomoko Ogura ,  Seiki Ogura

发明人： Nori Ogura ,  Tomoko Ogura ,  Seiki Ogura

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/06 ,  G11C7/04 ,  G11C7/06 ,  G11C7/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0466 ,  G11C16/10 ,  G11C2211/5647

摘要： Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.

摘要翻译： 描述了存储器单元的互补配对的方法。 这些方法包括互补对中的两个物理存储器单元，每个擦除块的互补对参考单元，以及存储多个数据位的物理互补对。

公开(公告)号：US08325542B2

公开(公告)日：2012-12-04

申请号：US12583743

申请日：2009-08-25

申请人： Nori Ogura ,  Tomoko Ogura ,  Seiki Ogura

发明人： Nori Ogura ,  Tomoko Ogura ,  Seiki Ogura

IPC分类号： G11C7/00

CPC分类号： G11C16/06 ,  G11C7/04 ,  G11C7/06 ,  G11C7/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0466 ,  G11C16/10 ,  G11C2211/5647

摘要： Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.

摘要翻译： 描述了存储器单元的互补配对的方法。 这些方法包括互补对中的两个物理存储器单元，每个擦除块的互补对参考单元，以及存储多个数据位的物理互补对。

公开(公告)号：US08089809B2

公开(公告)日：2012-01-03

申请号：US12802888

申请日：2010-06-16

申请人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

发明人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

IPC分类号： G11C16/04

CPC分类号： G11C16/0466 ,  G11C16/0475 ,  H01L27/115

摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

摘要翻译： 非易失性陷阱电荷存储单元选择在可编程逻辑应用中使用的逻辑互连晶体管，例如FPGA。 非挥发性捕获电荷元件是位于控制栅极下方并位于半导体衬底表面上的氧化物之上的绝缘体。 优选实施例是集成器件，其包括夹在两个非易失性陷阱电荷存储部分之间的字门部分，其中该集成器件连接在高偏压，低偏压和输出之间。 输出由连接到字栅极下方的通道的扩散形成。 两个存储部分的编程状态确定高偏压或低偏压是否耦合到连接到输出扩散的逻辑互连晶体管。

公开(公告)号：US07447077B2

公开(公告)日：2008-11-04

申请号：US11500115

申请日：2006-08-07

申请人： Tomoko Ogura ,  Nori Ogura ,  Seiki Ogura ,  Yoshitaka Baba

发明人： Tomoko Ogura ,  Nori Ogura ,  Seiki Ogura ,  Yoshitaka Baba

IPC分类号： G11C11/34

CPC分类号： G11C7/14 ,  G11C16/0475 ,  G11C16/28 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459

摘要： A reference circuit is described for creating a reference signal using a twin MONOS memory cell. A first portion of the twin MONOS memory cell connects to a charged and floating bit line a current source formed in a second portion of the twin MONOS cell that discharges the charged bit line to form a reference signal for a sense amplifier. The sense amplifier compares the reference signal to a signal from a selected memory cell upon which memory operations are being performed comprising read, erase verify and program verify.

摘要翻译： 描述了使用双MONOS存储单元创建参考信号的参考电路。 双MONOS存储器单元的第一部分连接到充电和浮置位线，形成在双MONOS单元的第二部分中的电流源，其对充电的位线进行放电以形成用于读出放大器的参考信号。 读出放大器将参考信号与来自执行存储器操作的所选存储器单元的信号进行比较，包括读取，擦除验证和程序验证。

公开(公告)号：US07046553B2

公开(公告)日：2006-05-16

申请号：US10371518

申请日：2003-02-20

申请人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

发明人： Seiki Ogura ,  Tomoko Ogura ,  Nori Ogura

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3459 ,  G11C16/0475 ,  G11C16/12 ,  G11C16/3454

摘要： In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.