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41.发明申请SHIFT REGISTER, DISPLAY-DRIVING CIRCUIT, DISPLAYING PANEL, AND DISPLAYING DEVICE 有权移位寄存器，显示驱动电路，显示面板和显示设备公开(公告)号：US20120081346A1
公开(公告)日：2012-04-05
申请号：US13377838
申请日：2010-03-18
CPC分类号： G11C19/28 , G09G3/3677 , G09G2310/063
摘要： Provided is a shift register of a display-driving circuit which carries out simultaneous selection of a plurality of signal lines by using a simultaneous selection signal. A stage of the shift register includes (i) a set-reset type flip-flop and (ii) a signal generating circuit which generates an output signal of the stage by selectively outputting a signal in response to an output of the flip-flop. The output signal of the stage (i) becomes active due to an activation of the simultaneous selection signal and then (ii) remains active while the simultaneous selection is being performed, and the output from the flip-flop is inactive during a period in which a setting signal and a resetting signal are both being active. This makes it possible to quickly carry out the simultaneous selection of all the signal lines and the initialization of the shift register.
摘要翻译： 提供了一种显示驱动电路的移位寄存器，其通过使用同时选择信号来执行多个信号线的同时选择。 移位寄存器的一级包括（i）设置复位型触发器和（ii）信号发生电路，其通过响应于触发器的输出选择性地输出信号来产生该级的输出信号。 由于同时选择信号的激活，阶段（i）的输出信号变为有效，然后（ii）在执行同时选择时保持有效，并且触发器的输出在其中 设定信号和复位信号均处于活动状态。 这使得可以快速地执行所有信号线的同时选择和移位寄存器的初始化。
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42.发明授权公开(公告)号：US08971478B2
公开(公告)日：2015-03-03
申请号：US13575490
申请日：2011-02-10
CPC分类号： G11C19/28 , G09G3/3677
摘要： A shift register includes a plurality of stages of unit circuits each including a flip-flop. Each of the unit circuits generates, by obtaining a sync signal in accordance with an output from the flip-flop, an output signal. The flip-flop includes a first switch and a second switch and a latch circuit for latching a signal supplied thereto and outputting the signal as the output from the flip-flop. A first shift direction signal is supplied to the latch circuit via the first switch, and the second shift direction signal is supplied to the latch circuit via the second switch. In each unit circuit other than those of the first and last stages, an output signal from a previous stage is supplied to a control terminal of the first switch, and an output signal from a subsequent stage is supplied to a control terminal of the second switch.
摘要翻译： 移位寄存器包括多个阶段的单元电路，每个单元电路包括一个触发器。 每个单元电路通过根据触发器的输出获得同步信号来产生输出信号。 触发器包括第一开关和第二开关以及用于锁存提供给其的信号的锁存电路，并将该信号作为触发器的输出输出。 第一移位方向信号通过第一开关提供给锁存电路，第二移位方向信号通过第二开关提供给锁存电路。 在除了第一级和最后级之外的每个单元电路中，来自前一级的输出信号被提供给第一开关的控制端，并且来自后级的输出信号被提供给第二开关的控制端 。
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公开(公告)号：US08860646B2
公开(公告)日：2014-10-14
申请号：US13395716
申请日：2010-05-18
IPC分类号： G09G3/36
CPC分类号： G09G3/3618 , G09G3/3614 , G09G3/3659 , G09G2300/0823 , G09G2300/0852
摘要： A memory liquid crystal display device includes a transistor (N1), a transistor (N2), a transistor (N3), a transistor (N4), a first storage capacitor (storage capacitor of an overlapping part of a capacitor electrode 37a and a CS line CSL(i)) connected to a pixel electrode (7), and a second storage capacitor (storage capacitor of an overlapping part of a capacitor electrode 37b and a CS extension section 10bb) connected to the pixel electrode (7) via the transistor (N2), the pixel electrode (7) being connected to (a) a source line (SL(j)) via the transistor (N1), (b) a data transfer control line (DT(i)) via the transistor (N4) and the third transistor, (c) a drain electrode (9a) of the transistor (N1) via a contact hole (13), and (d) a source electrode (8b) of the transistor (N2) and to a drain electrode (9c) of the transistor (N4), via a contact hole (14). This allows for improving a yield rate and for reducing malfunction caused by noise generated between signal lines, in a memory liquid crystal display device.
摘要翻译： 存储液晶显示装置包括晶体管（N1），晶体管（N2），晶体管（N3），晶体管（N4），第一存储电容器（电容器电极37a的重叠部分的存储电容器和CS 连接到像素电极（7）的线CSL（i））和连接到像素电极（7）的第二存储电容器（电容器电极37b和CS延伸部分10bb的重叠部分的存储电容器） （N2），经由晶体管（N1）与（a）源极线（SL（j））连接的像素电极（7），（b）经由晶体管的数据传输控制线（DT（i） N4）和第三晶体管，（c）经由接触孔（13）的晶体管（N1）的漏电极（9a）和（d）晶体管（N2）的源电极（8b）和漏极 晶体管（N4）的电极（9c）经由接触孔（14）。 这允许在存储器液晶显示装置中提高成品率并减少由信号线之间产生的噪声引起的故障。
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公开(公告)号：US08791895B2
公开(公告)日：2014-07-29
申请号：US13395536
申请日：2010-05-26
申请人： Makoto Yokoyama , Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Seijirou Gyouten , Shuji Nishi
发明人： Makoto Yokoyama , Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Seijirou Gyouten , Shuji Nishi
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G02F1/13624 , G09G2300/043 , G09G2300/0819 , G09G2300/0852 , G09G2300/0876 , G09G2310/063 , G09G2310/08 , G09G2320/0219 , G09G2320/0247 , G09G2340/0428
摘要： In a memory liquid crystal display device, a potential of a storage capacitor line signal (CS) supplied to the CS lines (CSL(i)) are once decreased (ΔVcs) while the gate lines (GL(i)) are made simultaneously active (period t4, period t10) in the data holding period (T2), and the potential of the storage capacitor line signal (CS) is made back to its original potential while the gate lines (GL(i)) are made simultaneously inactive and the refresh output control lines (RC(i)) are made active (period t5, period t11). This reduces flicker, thereby allowing for improvement in display quality of the memory liquid crystal display device.
摘要翻译： 在存储器液晶显示装置中，提供给CS线（CSL（i））的辅助电容配线信号（CS）的电位在制作栅极线（GL（i））时一度减小（＆Dgr; Vcs） 在数据保持期间（T2）中同时有效（周期t4，期间t10），并且保持电容配线信号（CS）的电位恢复到原来的电位，而同时进行栅极线（GL（i）） 并且刷新输出控制线（RC（i））被激活（时段t5，周期t11）。 这减少了闪烁，从而可以提高存储器液晶显示装置的显示质量。
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公开(公告)号：US08743042B2
公开(公告)日：2014-06-03
申请号：US13395697
申请日：2010-04-23
CPC分类号： G09G3/3607 , G09G3/3614 , G09G3/3618 , G09G3/3655 , G09G3/3659 , G09G2300/0814 , G09G2300/0823 , G09G2300/0842 , G09G2300/0852 , G09G2300/0861 , G09G2320/0219 , G09G2330/021 , G09G2330/022
摘要： Provided are a display device capable of preventing image noise arising from changes in potential of a common electrode and auxiliary capacitor lines at the time of a switch between a normal mode and a memory mode and a method for driving such a display device. In a case where it is necessary to cause the common electrode and the auxiliary capacitor lines to change in potential along with a switch between the normal mode and the memory mode, the change in potential is made while electrically connecting a node of each memory circuit to a corresponding source line with the corresponding source line having its potential fixed and with the memory circuit having its a switch circuit in a conductive state.
摘要翻译： 提供了能够防止在正常模式和存储模式之间的切换时由公共电极和辅助电容器线的电位变化引起的图像噪声的显示装置以及用于驱动这种显示装置的方法。 在需要使公共电极和辅助电容线与正常模式和存储模式之间的切换一起改变电位的情况下，在将每个存储器电路的节点电连接到 对应的源极线，其相应的源极线具有其电位固定，并且存储电路具有其导通状态的开关电路。
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公开(公告)号：US20120249499A1
公开(公告)日：2012-10-04
申请号：US13513017
申请日：2010-10-07
IPC分类号： G06F3/038
CPC分类号： G09G3/006 , G09G3/3611 , G09G3/3688 , G09G2310/0297 , G09G2330/12
摘要： A one-input and three-output demultiplexer that includes sampling switches for sampling a video signal is provided at one end side of source bus lines, and a one-input and three-output demultiplexer that includes test switches provided corresponding to sampling switches and that uses a test video signal as an input signal is provided at the other end side of the source bus lines. When an any control signal out of three control signals for controlling states of a sampling switch and a test switch is defined as a target control signal, a source bus line connected to the sampling switch which is set to an on state by the target control signal and a source bus line connected to the test switch which is set to an on state by the target control signal are different.
摘要翻译： 在源总线的一端提供包括用于采样视频信号的采样开关的单输入和三输出解复用器，以及包括与采样开关相对应的测试开关的单输入和三输出解复用器，并且 使用测试视频信号作为输入信号设置在源总线的另一端。 当将用于控制采样开关和测试开关的状态的三个控制信号中的任何控制信号定义为目标控制信号时，连接到通过目标控制信号被设置为导通状态的采样开关的源极总线 并且连接到由目标控制信号设置为接通状态的测试开关的源极总线不同。
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公开(公告)号：US20120086703A1
公开(公告)日：2012-04-12
申请号：US13375778
申请日：2010-02-23
CPC分类号： G09G3/3655 , G09G3/3614 , G09G3/3677 , G09G2300/0852 , G09G2300/0876
摘要： A display driving circuit for driving a liquid crystal display panel includes a shift register including a plurality of shift register circuits provided in such a way as to correspond to a plurality of gate lines, respectively, the display driving circuit having latch circuits provided in such a way as to correspond one-by-one to the shift register circuits, a polarity signal being inputted to the latch circuits. When a internal signal generated by a shift register circuit becomes active, a latch circuit loads and retains the polarity signal, and an output from the latch circuit is supplied to a CS bus line. The internal signal becomes active before a first vertical scanning period of a display picture.
摘要翻译： 用于驱动液晶显示面板的显示驱动电路包括：移位寄存器，其包括分别以对应于多个栅极线的方式设置的多个移位寄存器电路，显示驱动电路具有设置在其中的锁存电路 方式一对一地对应到移位寄存器电路，极性信号被输入到锁存电路。 当由移位寄存器电路产生的内部信号变为有效时，锁存电路加载并保持极性信号，并且将锁存电路的输出提供给CS总线。 内部信号在显示图像的第一垂直扫描周期之前变为有效。
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公开(公告)号：US20100245328A1
公开(公告)日：2010-09-30
申请号：US12734376
申请日：2008-08-21
IPC分类号： G09G5/00
CPC分类号： G09G3/3655 , G09G3/3614 , G09G3/3677 , G09G2300/0876 , G09G2310/0286 , G09G2320/0209 , G09G2320/0219 , G11C19/184
摘要： In a storage capacitor line drive circuit driving a storage capacitor line of an active-matrix display device and driven by outputs of a scanning signal line drive circuit, at least one (VSS) of a high-potential supply voltage (VDD) and a low-potential supply voltage (VSS) differs from a supply voltage (GVSS) of a corresponding logical level of the scanning signal line drive circuit, the high-potential supply voltage and the low-potential supply voltage being used for generating a signal voltage of a preceding stage to an output stage. This makes it possible to achieve a storage capacitor line drive circuit capable of avoiding malfunctioning even in a case where the storage capacitor line drive circuit receives noise from a scanning signal line, and a display device including the storage capacitor line drive circuit.
摘要翻译： 在驱动有源矩阵型显示装置的辅助电容线并由扫描信号线驱动电路的输出驱动的辅助电容线驱动电路中，高电位电源电压（VDD）和低电位 电位电压（VSS）与扫描信号线驱动电路的相应逻辑电平的电源电压（GVSS）不同，高电位电源电压和低电位电源电压用于产生信号电压 前一阶段到产出阶段。 这使得即使在存储电容器线路驱动电路从扫描信号线接收到噪声的情况下也可以实现能够避免故障的存储电容器线路驱动电路，以及包括辅助电容线驱动电路的显示装置。
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公开(公告)号：US20100244946A1
公开(公告)日：2010-09-30
申请号：US12734044
申请日：2008-08-26
IPC分类号： H01L25/00
CPC分类号： G09G3/3677 , G09G3/3655 , G09G2310/0286 , G09G2310/0289 , G09G2310/0291 , G11C19/184 , G11C19/28 , H03K17/063 , H03K17/165 , H03K17/693
摘要： A circuit is constituted by a plurality of n-channel-type transistors, the circuit including: among the plurality of transistors, a transistor including a drain terminal for receiving a voltage of VDD, a source terminal, and a gate terminal for receiving an input signal; among the plurality of transistors, a transistor including a drain terminal for receiving the voltage of VDD, a source terminal connected to an output terminal, and a gate terminal connected to the source terminal of the transistor; and a capacitor provided between a node and a clock terminal for receiving a clock signal. In at least one embodiment, the clock signal inputted into the clock terminal has a frequency higher than that of an output signal outputted from the output terminal. Therefore, it is possible to provide: a semiconductor device constituted by transistors of the same conductivity type, which semiconductor device can output a stable signal by preventing a reduction in electric potential level; and a display device including the semiconductor device.
摘要翻译： 电路由多个n沟道型晶体管构成，所述电路包括：在所述多个晶体管中，包括用于接收VDD电压的漏极端子的晶体管，源极端子和用于接收输入的栅极端子 信号; 在多个晶体管中，包括用于接收VDD的电压的漏极端子，连接到输出端子的源极端子和连接到晶体管的源极端子的栅极端子的晶体管; 以及设置在节点和时钟端子之间用于接收时钟信号的电容器。 在至少一个实施例中，输入到时钟端的时钟信号的频率高于从输出端输出的输出信号的频率。 因此，可以提供：由相同导电类型的晶体管构成的半导体器件，该半导体器件可以通过防止电位电平的降低而输出稳定的信号; 以及包括半导体器件的显示装置。
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公开(公告)号：US20100214206A1
公开(公告)日：2010-08-26
申请号：US12734218
申请日：2008-08-26
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/06 , G09G2330/08 , G11C19/28
摘要： At least one embodiment the present invention a plurality of unit circuits connected in multiple stages, to normal operation when the unit circuits are simultaneously turned on to output high-level output signals. When a shift register malfunctions, so that output signals provided by previous- and subsequent-stage unit circuits are simultaneously set to high level, malfunction restoration circuits and included in a unit circuit detect the malfunction in at least one embodiment. The malfunction restoration circuit provides a high voltage to a node, thereby forcibly pulling down an output signal. Also, the malfunction restoration circuit forcibly discharges another node, so that a charge accumulated in a capacitance is released. As a result, the shift register in malfunction can be instantaneously restored to normal operation. At least one embodiment of the present invention is suitable for driver circuits or suchlike of display devices and imaging devices.
摘要翻译： 本发明的至少一个实施例是多个单元电路以多级连接，当单元电路同时导通以输出高电平输出信号时，进行正常操作。 当移位寄存器发生故障时，使得由前一级和后级单元电路提供的输出信号同时设置为高电平，故障恢复电路并包括在单元电路中，在至少一个实施例中检测故障。 故障恢复电路向节点提供高电压，从而强制拉下输出信号。 此外，故障恢复电路强制地对另一个节点进行放电，从而释放在电容中累积的电荷。 结果，故障中的移位寄存器可以立即恢复正常运行。 本发明的至少一个实施例适用于诸如显示装置和成像装置的驱动电路等。
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