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公开(公告)号：US09230496B2
公开(公告)日：2016-01-05
申请号：US13981219
申请日：2012-01-23
Applicant: Seijirou Gyouten , Makoto Yokoyama , Takahiro Yamaguchi , Shige Furuta
Inventor： Seijirou Gyouten , Makoto Yokoyama , Takahiro Yamaguchi , Shige Furuta
CPC classification number: G09G3/3648 , G09G3/3611 , G09G3/3685 , G09G2310/0297
Abstract: This display device has a demultiplexer (501) formed on a liquid crystal panel, the demultiplexer including three switching elements SW1 to SW3 for time-division drive, which are connected to video signal lines SL1 to SL3. Here, the number of switching control signal lines for transmitting switching control signals GS1 to GS6 to be provided to switching elements coupled to the video signal lines is six, which is twice the number of time divisions, and switching control signals (e.g., GS1 and GS4) with the same timing are individually transmitted by two switching control signal lines, so that the number of switching elements to be coupled to the switching control signal lines as loads can be halved, resulting in reduced waveform rounding of the control signals.
Abstract translation: 该显示装置具有形成在液晶面板上的解复用器（501），该解复用器包括与视频信号线SL1〜SL3连接的三个时分驱动用开关元件SW1〜SW3。 这里，用于发送提供给耦合到视频信号线的开关元件的开关控制信号GS1至GS6的开关控制信号线的数量是时间分割数的两倍的开关控制信号线的数量和切换控制信号（例如，GS1和 GS4）通过两个开关控制信号线分别发送，从而将作为负载耦合到开关控制信号线的开关元件的数量减半，导致控制信号的减少的波形舍入。
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公开(公告)号：US08970565B2
公开(公告)日：2015-03-03
申请号：US13378233
申请日：2010-03-18
Applicant: Takuya Hachida , Yuhichiroh Murakami , Shige Furuta , Makoto Yokoyama , Yasushi Sasaki
Inventor： Takuya Hachida , Yuhichiroh Murakami , Shige Furuta , Makoto Yokoyama , Yasushi Sasaki
CPC classification number: G11C19/28 , G09G3/3677 , G09G2310/063
Abstract: A stage of the shift register has (i) a set-reset type flip-flop which receives an initialization signal and (ii) a signal generating circuit which receives a simultaneous selection signal and which generates an output signal by use of an output of the flip-flop. In at least one example embodiment, the output of the flip-flop becomes inactive regardless of whether a setting signal and a resetting signal are active or inactive, as long as the initialization signal is active. The initialization signal becomes active before the end of the simultaneous selection, and then becomes inactive after the end of the simultaneous selection. This makes it possible to stabilize operation of the shift register after the end of simultaneous selection of a plurality of signal lines carried out by the display driving circuit at a predetermined timing.
Abstract translation: 移位寄存器的一级具有（i）接收初始化信号的设置复位型触发器，以及（ii）接收同时选择信号并且通过使用输出信号产生输出信号的信号发生电路 拖鞋。 在至少一个示例性实施例中，只要初始化信号有效，触发器的输出就会变得无效，而不管设置信号和复位信号是有效还是无效。 初始化信号在同时选择结束之前变为有效，然后在同时选择结束后变为无效。 这使得可以在预定定时同时选择由显示驱动电路执行的多条信号线结束之后稳定移位寄存器的操作。
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公开(公告)号：US20130300722A1
公开(公告)日：2013-11-14
申请号：US13981219
申请日：2012-01-23
Applicant: Seijirou Gyouten , Makoto Yokoyama , Takahiro Yamaguchi , Shige Furuta
Inventor： Seijirou Gyouten , Makoto Yokoyama , Takahiro Yamaguchi , Shige Furuta
IPC: G09G3/36
CPC classification number: G09G3/3648 , G09G3/3611 , G09G3/3685 , G09G2310/0297
Abstract: This display device has a demultiplexer (501) formed on a liquid crystal panel, the demultiplexer including three switching elements SW1 to SW3 for time-division drive, which are connected to video signal lines SL1 to SL3. Here, the number of switching control signal lines for transmitting switching control signals GS1 to GS6 to be provided to switching elements coupled to the video signal lines is six, which is twice the number of time divisions, and switching control signals (e.g., GS1 and GS4) with the same timing are individually transmitted by two switching control signal lines, so that the number of switching elements to be coupled to the switching control signal lines as loads can be halved, resulting in reduced waveform rounding of the control signals.
Abstract translation: 该显示装置具有形成在液晶面板上的解复用器（501），该解复用器包括与视频信号线SL1〜SL3连接的三个时分驱动用开关元件SW1〜SW3。 这里，用于发送提供给耦合到视频信号线的开关元件的开关控制信号GS1至GS6的开关控制信号线的数量是时间分割数的两倍的开关控制信号线的数量和切换控制信号（例如GS1和 GS4）通过两个开关控制信号线分别发送，从而将作为负载耦合到开关控制信号线的开关元件的数量减半，导致控制信号的减少的波形舍入。
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公开(公告)号：US20120200614A1
公开(公告)日：2012-08-09
申请号：US13501368
申请日：2010-06-02
Applicant: Etsuo Yamamoto , Shige Furuta , Yuhichiroh Murakami , Seijirou Gyouten
Inventor： Etsuo Yamamoto , Shige Furuta , Yuhichiroh Murakami , Seijirou Gyouten
CPC classification number: G09G3/3614 , G09G3/3655 , G09G3/3674 , G09G3/3677 , G09G2300/0876 , G09G2310/0264 , G09G2310/0286 , G09G2310/08 , G09G2320/0219 , G09G2320/0233 , G09G2340/0407
Abstract: In a display device (i) which carries out a display based on a video signal whose resolution has been converted to higher resolution (high-resolution conversion driving) and (ii) which carries out CC driving, when the resolution of the video signal is converted by a factor of 2 (double-size display), assuming that a direction in which the gate lines extend is a row-wise direction, signal potentials having the same polarity and the same gray scale are supplied to pixel electrodes included in respective two pixels that correspond to two adjacent gate lines and that are adjacent to each other in the column-wise direction (scanning direction), and a direction of change in the signal potentials written to the pixel electrodes from the source lines varies every two adjacent rows according to the polarities of the signal potentials.
Abstract translation: 在基于分辨率被转换为更高分辨率（高分辨率转换驱动）的视频信号和执行CC驱动的（ii））执行显示的显示装置（i）中，当视频信号的分辨率为 转换为2倍（双倍尺寸显示），假设栅极线延伸的方向是行方向，具有相同极性和相同灰度的信号电位被提供给包括在相应两个中的像素电极 对应于两个相邻的栅极线并且在列方向（扫描方向）上彼此相邻的像素，并且从源极线写入像素电极的信号电位的变化方向根据 到信号电位的极性。
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公开(公告)号：US20120200549A1
公开(公告)日：2012-08-09
申请号：US13395518
申请日：2010-04-23
Applicant: Yasushi Sasaki , Yuhichiroh Murakami , Shige Furuta , Seijirou Gyouten , Shuji Nishi
Inventor： Yasushi Sasaki , Yuhichiroh Murakami , Shige Furuta , Seijirou Gyouten , Shuji Nishi
CPC classification number: G09G3/3659 , G09G2300/0842 , G09G2300/0861 , G09G2320/0219 , G09G2330/022
Abstract: Provided is a display device which can prevent screen noise caused such that a potential of a common electrode is reversed after a memory mode enters from a refresh period to an entire write-in period, and a method for driving the display device. The memory mode includes (i) an entire write-in period in which a potential of the common electrode (COM) is fixed and the display data is written into all the memory circuits (node (PIX)) in each row and (ii) a refresh period in which the display data which has been written during the entire write-in period is refreshed at least once while the common electrode (COM) is driven. In the memory mode, the potential of the common electrode during the entire write-in period being a potential which the common electrode having been driven had at the end of a refresh period preceding the entire write-in period.
Abstract translation: 提供一种显示装置，其可以防止在从刷新周期进入整个写入周期之后引起公共电极的电位反转的屏幕噪声，以及用于驱动显示装置的方法。 存储模式包括：（i）公共电极（COM）的电位固定并将显示数据写入到每行的所有存储电路（节点（PIX））中的整个写入周期，以及（ii） 在驱动公共电极（COM）的过程中至少刷新一次整个写入周期期间已写入的显示数据的刷新周期。 在存储模式中，公共电极在整个写入周期期间的电位是已经被驱动的公共电极在整个写入周期之前的刷新周期结束时的电位。
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Patent Agency Ranking
公开(公告)号：US08223112B2
公开(公告)日：2012-07-17
申请号：US12734234
申请日：2008-08-18
Applicant: Hiroyuki Ohkawa , Shige Furuta , Yasushi Sasaki , Yuhichiroh Murakami
Inventor： Hiroyuki Ohkawa , Shige Furuta , Yasushi Sasaki , Yuhichiroh Murakami
CPC classification number: G11C19/28 , G09G3/20 , G09G3/3266 , G09G3/3275 , G09G3/3648 , G09G3/3674 , G09G3/3677 , G09G3/3685 , G09G3/3688 , G09G2300/0426 , G09G2310/0245 , G09G2310/0267 , G09G2310/0275 , G09G2310/0286 , G09G2310/0291
Abstract: At least one embodiment of the present invention is directed to, even when external noise is applied to a shift register during all-on operation, preventing through-current from flowing in unit circuits and also to prevent increase in load on all-on control signal lines. When a high-level all-on control signal is provided to a unit circuit of a shift register, a transistor T3 is brought into off-state, so that a transistor T2 cannot output an on-voltage to a first output terminal. However, a transistor T24 is brought into on-state, so that the first output terminal outputs an on-voltage to the exterior. On the other hand, a transistor T32 is brought into on-state, so that a second output terminal outputs an off-voltage to a unit circuit 11 in the next stage. At this time, the transistor T3 is kept in off-state, so that no through-current flows to the transistors T24 and T3.
Abstract translation: 本发明的至少一个实施例涉及即使当在全导通操作期间外部噪声被施加到移位寄存器时，也可以防止在单位电路中流过电流，并且还防止全通控制信号的负载增加 线条。 当向移位寄存器的单元电路提供高电平全通控制信号时，晶体管T3进入截止状态，晶体管T2不能向第一输出端子输出导通电压。 然而，晶体管T24进入导通状态，使得第一输出端子向外部输出导通电压。 另一方面，晶体管T32进入导通状态，使得第二输出端在下一级向单元电路11输出截止电压。 此时，晶体管T3保持截止状态，使得没有贯通电流流向晶体管T24和T3。
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7.发明申请MEMORY DEVICE, DISPLAY DEVICE EQUIPPED WITH MEMORY DEVICE, DRIVE METHOD FOR MEMORY DEVICE, AND DRIVE METHOD FOR DISPLAY DEVICE 有权存储装置，具有存储装置的显示装置，用于存储装置的驱动方法和用于显示装置的驱动方法公开(公告)号：US20120169753A1
公开(公告)日：2012-07-05
申请号：US13496027
申请日：2010-04-23
Applicant: Yuhichiroh Murakami , Shige Furuta , Yasushi Sasaki , Seijirou Gyouten , Shuji Nishi
Inventor： Yuhichiroh Murakami , Shige Furuta , Yasushi Sasaki , Seijirou Gyouten , Shuji Nishi
CPC classification number: G09G3/3659 , G09G2300/0417 , G09G2300/0823 , G09G2300/0842 , G09G2300/0861 , G09G2300/088 , G09G2330/022 , G11C11/405
Abstract: A memory device is provided which includes a memory circuit that allows a circuit which carries out a refresh operation to suitably carry out an original operation of the circuit even if an off-leakage current occurs in a transfer element used in a transfer section. A memory cell includes a switching circuit, a first retaining section, a transfer section, a second retaining section, a first control section, and a voltage supply, and the first control section is controlled to be in (i) a state in which the first control section carries out a first operation in which the first control section is in an active state or a non-active state and (ii) a state in which the first control section carries out a second operation.
Abstract translation: 提供了一种存储器件，其包括一个存储器电路，即使在转印部件中使用的转印元件中出现泄漏电流，允许进行刷新操作的电路适当地执行电路的原始操作。 存储单元包括开关电路，第一保持部分，转移部分，第二保持部分，第一控制部分和电压源，并且第一控制部分被控制为处于（i） 第一控制部分执行第一操作，其中第一控制部分处于活动状态或非活动状态，以及（ii）第一控制部分执行第二操作的状态。
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公开(公告)号：US20120086689A1
公开(公告)日：2012-04-12
申请号：US13377847
申请日：2010-02-28
Applicant: Shige Furuta , Etsuo Yamamoto , Yuhichiroh Murakami , Seijirou Gyouten
Inventor： Shige Furuta , Etsuo Yamamoto , Yuhichiroh Murakami , Seijirou Gyouten
CPC classification number: G09G3/3655 , G09G3/3614 , G09G3/3659 , G09G3/3677 , G09G2300/0852 , G09G2320/0247
Abstract: An embodiment of the present invention switches, in a display driving circuit of a liquid crystal display device which carries out CC driving, between a two-line reversal driving mode in which a polarity of a data signal supplied to a source line is reversed every two horizontal scanning periods and a one-line reversal driving mode in which a polarity of a data signal supplied to a source line is reversed every one horizontal scanning period. In at least one example embodiment, a polarity signal reverses its polarity every two horizontal scanning periods in the two-line reversal driving mode, and reverses its polarity every one horizontal scanning period in the one-line reversal driving mode.
Abstract translation: 本发明的一个实施例在执行CC驱动的液晶显示装置的显示驱动电路中，在提供给源极线的数据信号的极性每二次反转的两线反向驱动模式之间切换 水平扫描周期和提供给源极线的数据信号的极性在每一个水平扫描周期反转的单线反转驱动模式。 在至少一个示例性实施例中，极性信号在双线反向驱动模式中每两个水平扫描周期反转其极性，并且在单行反向驱动模式中每一个水平扫描周期反转其极性。
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公开(公告)号：US20100309184A1
公开(公告)日：2010-12-09
申请号：US12734595
申请日：2008-08-20
Applicant: Etsuo Yamamoto , Yasushi Sasaki , Yuhichiroh Murakami , Shige Furuta
Inventor： Etsuo Yamamoto , Yasushi Sasaki , Yuhichiroh Murakami , Shige Furuta
CPC classification number: G09G3/3677 , G09G2300/0408 , G09G2300/0426 , G09G2310/0289 , G11C19/28 , H01L27/124 , H03K17/161 , H03K17/162 , H03K17/687
Abstract: A circuit which is constituted by a plurality of n-channel transistors includes, in at least one embodiment, a transistor (T1) which has a drain terminal to which an input signal is supplied and a source terminal from which a output signal is supplied; and a transistor (T2) which has a drain terminal to which a control signal is supplied and a source terminal connected to a gate terminal of the transistor (T1). A gate terminal of the transistor (T2) is connected to the source terminal of the transistor (T2). With the arrangement, it is possible to provide (i) a semiconductor device which is constituted by transistors having an identical conductivity type and which is capable of reducing an influence of noise, and (ii) a display device including the semiconductor device.
Abstract translation: 在至少一个实施例中，由多个n沟道晶体管构成的电路包括具有供给输入信号的漏极端子和提供输出信号的源极端子的晶体管（T1）; 以及具有提供控制信号的漏极端子和与晶体管（T1）的栅极端子连接的源极端子的晶体管（T2）。 晶体管（T2）的栅极端子连接到晶体管（T2）的源极端子。 通过该结构，可以提供（i）由具有相同导电类型并能够减小噪声影响的晶体管构成的半导体器件，以及（ii）包括半导体器件的显示器件。
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公开(公告)号：US20100259525A1
公开(公告)日：2010-10-14
申请号：US12734234
申请日：2008-08-18
Applicant: Hiroyuki Ohkawa , Shige Furuta , Yasushi Sasaki , Yuhichiroh Murakami
Inventor： Hiroyuki Ohkawa , Shige Furuta , Yasushi Sasaki , Yuhichiroh Murakami
CPC classification number: G11C19/28 , G09G3/20 , G09G3/3266 , G09G3/3275 , G09G3/3648 , G09G3/3674 , G09G3/3677 , G09G3/3685 , G09G3/3688 , G09G2300/0426 , G09G2310/0245 , G09G2310/0267 , G09G2310/0275 , G09G2310/0286 , G09G2310/0291
Abstract: At least one embodiment of the present invention is directed to, even when external noise is applied to a shift register during all-on operation, preventing through-current from flowing in unit circuits and also to prevent increase in load on all-on control signal lines. When a high-level all-on control signal is provided to a unit circuit of a shift register, a transistor T3 is brought into off-state, so that a transistor T2 cannot output an on-voltage to a first output terminal. However, a transistor T24 is brought into on-state, so, that the first output terminal outputs an on-voltage to the exterior. On the other hand, a transistor T32 is brought into on-state, so that a second output terminal outputs an off-voltage to a unit circuit 11 in the next stage. At this time, the transistor T3 is kept in off-state, so that no through-current flows to the transistors T24 and T3. At least one embodiment of the present invention is suitable for driver circuits or suchlike of display devices and imaging devices.
Abstract translation: 本发明的至少一个实施例涉及即使当在全导通操作期间外部噪声被施加到移位寄存器时，也可以防止贯通电流在单元电路中流动，并且还防止全导通控制信号上的负载增加 线条。 当向移位寄存器的单元电路提供高电平全通控制信号时，晶体管T3进入截止状态，晶体管T2不能向第一输出端子输出导通电压。 然而，晶体管T24进入导通状态，因此，第一输出端子向外部输出导通电压。 另一方面，晶体管T32进入导通状态，使得第二输出端在下一级向单元电路11输出截止电压。 此时，晶体管T3保持截止状态，使得没有贯通电流流向晶体管T24和T3。 本发明的至少一个实施例适用于诸如显示装置和成像装置的驱动电路等。
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