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41.发明申请Flip-Flop, Shift Register, Display Drive Circuit, Display Apparatus, And Display Panel 有权触发器，移位寄存器，显示驱动电路，显示设备和显示面板公开(公告)号：US20120092323A1
公开(公告)日：2012-04-19
申请号：US13378214
申请日：2010-03-26
CPC分类号： G09G3/3677 , G09G3/3655 , G09G3/3688 , G09G2300/0876 , G09G2310/0286 , G11C19/28 , H03K3/356104
摘要： A flip-flop includes: a first, second, third, and fourth transistors; input terminals; and first and second output terminals, the first and second transistors constituting a first CMOS circuit such that gate terminals are connected and drain terminals are connected, the third and fourth transistors constituting a second CMOS circuit such that gate terminals are connected and drain terminals are connected, the first output terminal connected to a gate side of the first CMOS circuit and a drain side of the second CMOS circuit, the second output terminal connected to a gate side of the second CMOS circuit and a drain side of the first CMOS circuit, at least one input transistor included in the group of the first through fourth transistors, a source terminal of the input transistor being connected to one of the input terminals. This can provide a further compact flip-flop.
摘要翻译： 触发器包括：第一，第二，第三和第四晶体管; 输入端子; 以及第一和第二输出端子，构成第一CMOS电路的第一和第二晶体管使得栅极端子连接并且漏极端子连接，第三和第四晶体管构成第二CMOS电路，使得栅极端子连接并且漏极端子被连接 连接到第一CMOS电路的栅极侧的第一输出端子和第二CMOS电路的漏极侧，第二输出端子连接到第二CMOS电路的栅极侧和第一CMOS电路的漏极侧， 包括在第一至第四晶体管组中的至少一个输入晶体管，输入晶体管的源极端子连接到输入端子之一。 这可以提供更紧凑的触发器。
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42.发明授权Shift register, display-driving circuit, displaying panel, and displaying device 有权移位寄存器，显示驱动电路，显示面板和显示设备公开(公告)号：US09047842B2
公开(公告)日：2015-06-02
申请号：US13377855
申请日：2010-03-18
CPC分类号： G09G3/3677 , G09G3/3614 , G09G3/3655 , G09G2310/0245 , G09G2310/0286 , G09G2310/063 , G09G2320/0233 , G09G2330/026 , G09G2330/027 , G11C19/28 , H03K3/356182
摘要： Disclosed is a shift register for use in a display driving circuit that simultaneously selects signal lines, including, in a stage thereof: a flip-flop including an initialization terminal; and a signal generating circuit that receives a simultaneous selection signal and that generates an output signal of the stage by use of an output of the flip-flop, wherein: the output signal of the stage becomes active due to an activation of the simultaneous selection signal so as to be active during a period of the simultaneous selection; the output of the flip-flop is non-active while the initialization terminal, a set terminal, and a reset terminal of the flip-flop; and the initialization terminal of the flip-flop receives the simultaneous selection signal. This shift register makes it possible to downsize various drivers.
摘要翻译： 公开了一种在显示驱动电路中使用的移位寄存器，其同时选择信号线，其中包括：其包括初始化端子的触发器; 以及信号发生电路，其接收同时选择信号，并且通过使用所述触发器的输出来产生所述级的输出信号，其中：所述级的输出信号由于同时选择信号的激活而变为有效 以便在同时选择期间活跃; 触发器的输出在触发器的初始化端子，设定端子和复位端子处于非有效状态; 并且触发器的初始化端子接收同时选择信号。 该移位寄存器使得可以减小各种驱动程序的尺寸。
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43.发明授权Flip-flop, shift register, display drive circuit, display apparatus, and display panel 有权触发器，移位寄存器，显示驱动电路，显示装置和显示面板公开(公告)号：US09014326B2
公开(公告)日：2015-04-21
申请号：US13378214
申请日：2010-03-26
CPC分类号： G09G3/3677 , G09G3/3655 , G09G3/3688 , G09G2300/0876 , G09G2310/0286 , G11C19/28 , H03K3/356104
摘要： A flip-flop includes: a first, second, third, and fourth transistors; input terminals; and first and second output terminals, the first and second transistors constituting a first CMOS circuit such that gate terminals are connected and drain terminals are connected, the third and fourth transistors constituting a second CMOS circuit such that gate terminals are connected and drain terminals are connected, the first output terminal connected to a gate side of the first CMOS circuit and a drain side of the second CMOS circuit, the second output terminal connected to a gate side of the second CMOS circuit and a drain side of the first CMOS circuit, at least one input transistor included in the group of the first through fourth transistors, a source terminal of the input transistor being connected to one of the input terminals. This can provide a further compact flip-flop.
摘要翻译： 触发器包括：第一，第二，第三和第四晶体管; 输入端子; 以及第一和第二输出端子，构成第一CMOS电路的第一和第二晶体管使得栅极端子连接并且漏极端子连接，第三和第四晶体管构成第二CMOS电路，使得栅极端子连接并且漏极端子被连接 连接到第一CMOS电路的栅极侧的第一输出端子和第二CMOS电路的漏极侧，第二输出端子连接到第二CMOS电路的栅极侧和第一CMOS电路的漏极侧， 包括在第一至第四晶体管组中的至少一个输入晶体管，输入晶体管的源极端子连接到输入端子之一。 这可以提供更紧凑的触发器。
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公开(公告)号：US08890856B2
公开(公告)日：2014-11-18
申请号：US13375311
申请日：2010-02-24
CPC分类号： G09G3/3677 , G09G3/3614 , G09G3/3655 , G09G2300/0852 , G09G2300/0876 , G09G2310/0286
摘要： A display driving circuit that carries out CC driving is configured such that retaining circuits are provided in such a way as to correspond one-by-one to their respective stages of a shift register, that a polarity signal CMI is inputted to each of the latch circuits, that when an internal signal Mn generated by a shift register at the nth stage becomes active, a latch circuit corresponding to the nth stage loads and retains the polarity signal CMI, that an output signal SRBOn from the shift register at the nth stage is supplied as a scanning signal to a gate line connected to pixels corresponding to the (n+1)th stage, and that an output from latch circuit corresponding to the nth stage is supplied as CSOUTn to a CS bus line forming capacitors with pixel electrodes of pixels corresponding to the nth stage.
摘要翻译： 执行CC驱动的显示驱动电路被配置为使得保持电路以与移位寄存器的各个级逐个对应的方式被提供，极性信号CMI被输入到每个锁存器 电路，当第n级的移位寄存器产生的内部信号Mn变为有效时，对应于第n级的锁存电路加载并保持极性信号CMI，来自第n级的移位寄存器的输出信号SRB0n为 作为扫描信号提供给连接到对应于第（n + 1）级的像素的栅极线，并且将与第n级相对应的锁存电路的输出作为CSOUTn提供给形成具有像素电极的电容器的CS总线 对应于第n级的像素。
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公开(公告)号：US08587572B2
公开(公告)日：2013-11-19
申请号：US12734376
申请日：2008-08-21
CPC分类号： G09G3/3655 , G09G3/3614 , G09G3/3677 , G09G2300/0876 , G09G2310/0286 , G09G2320/0209 , G09G2320/0219 , G11C19/184
摘要： In a storage capacitor line drive circuit driving a storage capacitor line of an active-matrix display device and driven by outputs of a scanning signal line drive circuit, at least one (VSS) of a high-potential supply voltage (VDD) and a low-potential supply voltage (VSS) differs from a supply voltage (GVSS) of a corresponding logical level of the scanning signal line drive circuit, the high-potential supply voltage and the low-potential supply voltage being used for generating a signal voltage of a preceding stage to an output stage. This makes it possible to achieve a storage capacitor line drive circuit capable of avoiding malfunctioning even in a case where the storage capacitor line drive circuit receives noise from a scanning signal line, and a display device including the storage capacitor line drive circuit.
摘要翻译： 在驱动有源矩阵型显示装置的辅助电容线并由扫描信号线驱动电路的输出驱动的辅助电容线驱动电路中，高电位电源电压（VDD）和低电位 电位电压（VSS）与扫描信号线驱动电路的相应逻辑电平的电源电压（GVSS）不同，高电位电源电压和低电位电源电压用于产生信号电压 前一阶段到产出阶段。 这使得即使在存储电容器线路驱动电路从扫描信号线接收到噪声的情况下也可以实现能够避免故障的存储电容器线路驱动电路，以及包括辅助电容线驱动电路的显示装置。
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公开(公告)号：US20130100105A1
公开(公告)日：2013-04-25
申请号：US13806878
申请日：2011-06-23
IPC分类号： G09G3/36
CPC分类号： G09G3/3674 , G09G3/3614 , G09G3/3648 , G09G3/3655 , G09G3/3677
摘要： A signal generator circuit of the present invention is a signal generator circuit for use in a display device, the display device including (a) a pixel having a pixel electrode, (b) an electric conductor with which the pixel electrode forms a capacitor, (c) a data signal line driving circuit which outputs a data signal whose polarity is reversed for each n horizontal scanning period(s), where n is a natural number, and (d) a scanning signal line driving circuit which outputs scanning signals corresponding to respective stages, said signal generator circuit generating a drive signal supplied to the electric conductor, wherein: said signal generator circuit comprises flip flops corresponding to the respective stages, each flip flop including a gate circuit and a latch circuit; and in regard to one flip flop corresponding to one of the stages, (i) the gate circuit is supplied with a signal synchronized with a scanning signal corresponding to a preceding stage of the one of the stages, and a signal synchronized with a scanning signal corresponding to a subsequent stage of the one of the stages, (ii) the latch circuit is supplied with a polarity signal whose polarity is reversed for each n horizontal scanning period(s) via the gate circuit, and (iii) the drive signal of the one of the stages is generated in accordance with an output of the one flip flop. With the arrangement, it is possible to provide, with use of a simple configuration, a driver circuit for use in a liquid crystal display device which carries out CC (charge coupling) driving or COM driving.
摘要翻译： 本发明的信号发生器电路是用于显示装置的信号发生器电路，该显示装置包括：（a）具有像素电极的像素，（b）像素电极与电容器形成的电导体; c）数据信号线驱动电路，其输出对于每个n个水平扫描周期的极性反转的数据信号，其中n是自然数，以及（d）扫描信号线驱动电路，其输出与 所述信号发生器电路产生提供给所述电导体的驱动信号，其中：所述信号发生器电路包括对应于各个级的触发器，每个触发器包括门电路和锁存电路; 并且对于与其中一个级相对应的一个触发器，（i）门电路被提供与与该级中的一级的前级相对应的扫描信号同步的信号，以及与扫描信号同步的信号 对应于所述一级的后续级，（ii）锁存电路经由门电路为每个n个水平扫描周期极性反转极性信号，以及（iii）驱动信号 根据一个触发器的输出产生一个级。 通过这种布置，可以使用简单的配置来提供用于执行CC（电荷耦合）驱动或COM驱动的液晶显示装置中的驱动电路。
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公开(公告)号：US20120086686A1
公开(公告)日：2012-04-12
申请号：US13375311
申请日：2010-02-24
CPC分类号： G09G3/3677 , G09G3/3614 , G09G3/3655 , G09G2300/0852 , G09G2300/0876 , G09G2310/0286
摘要： A display driving circuit that carries out CC driving is configured such that retaining circuits are provided in such a way as to correspond one-by-one to their respective stages of a shift register, that a polarity signal CMI is inputted to each of the latch circuits, that when an internal signal Mn generated by a shift register at the nth stage becomes active, a latch circuit corresponding to the nth stage loads and retains the polarity signal CMI, that an output signal SRBOn from the shift register at the nth stage is supplied as a scanning signal to a gate line connected to pixels corresponding to the (n+1)th stage, and that an output from latch circuit corresponding to the nth stage is supplied as CSOUTn to a CS bus line forming capacitors with pixel electrodes of pixels corresponding to the nth stage.
摘要翻译： 执行CC驱动的显示驱动电路被配置为使得保持电路以与移位寄存器的各个级逐个对应的方式被提供，极性信号CMI被输入到每个锁存器 电路，当第n级的移位寄存器产生的内部信号Mn变为有效时，对应于第n级的锁存电路加载并保持极性信号CMI，来自第n级的移位寄存器的输出信号SRB0n为 作为扫描信号提供给连接到与第（n + 1）级相对应的像素的栅极线，并且将与第n级对应的锁存电路的输出作为CSOUTn提供给形成具有像素电极的电容器的CS总线 对应于第n级的像素。
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公开(公告)号：US20100141641A1
公开(公告)日：2010-06-10
申请号：US12733117
申请日：2008-05-15
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.
摘要翻译： 在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。 通过使用两相时钟信号并且其高电平周期彼此不重叠，复位信号产生电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平 进入高层。 在复位信号为高电平的期间，晶体管T3，T4进行节点的放电，输出信号的下拉。 因此，可以获得省电移位寄存器，其将正常状态下的输出信号固定在低电平，而不允许通流通过。
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公开(公告)号：US08493312B2
公开(公告)日：2013-07-23
申请号：US13571608
申请日：2012-08-10
IPC分类号： G09G3/36
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.
摘要翻译： 在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。 通过使用两相时钟信号并且其高电平周期彼此不重叠，复位信号产生电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平 进入高层。 在复位信号为高电平的期间，晶体管T3，T4进行节点的放电，输出信号的下拉。 因此，可以获得省电移位寄存器，其将正常状态下的输出信号固定在低电平，而不允许通流通过。
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公开(公告)号：US20120249499A1
公开(公告)日：2012-10-04
申请号：US13513017
申请日：2010-10-07
IPC分类号： G06F3/038
CPC分类号： G09G3/006 , G09G3/3611 , G09G3/3688 , G09G2310/0297 , G09G2330/12
摘要： A one-input and three-output demultiplexer that includes sampling switches for sampling a video signal is provided at one end side of source bus lines, and a one-input and three-output demultiplexer that includes test switches provided corresponding to sampling switches and that uses a test video signal as an input signal is provided at the other end side of the source bus lines. When an any control signal out of three control signals for controlling states of a sampling switch and a test switch is defined as a target control signal, a source bus line connected to the sampling switch which is set to an on state by the target control signal and a source bus line connected to the test switch which is set to an on state by the target control signal are different.
摘要翻译： 在源总线的一端提供包括用于采样视频信号的采样开关的单输入和三输出解复用器，以及包括与采样开关相对应的测试开关的单输入和三输出解复用器，并且 使用测试视频信号作为输入信号设置在源总线的另一端。 当将用于控制采样开关和测试开关的状态的三个控制信号中的任何控制信号定义为目标控制信号时，连接到通过目标控制信号被设置为导通状态的采样开关的源极总线 并且连接到由目标控制信号设置为接通状态的测试开关的源极总线不同。
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