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公开(公告)号：US20100141641A1
公开(公告)日：2010-06-10
申请号：US12733117
申请日：2008-05-15
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.
摘要翻译： 在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。 通过使用两相时钟信号并且其高电平周期彼此不重叠，复位信号产生电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平 进入高层。 在复位信号为高电平的期间，晶体管T3，T4进行节点的放电，输出信号的下拉。 因此，可以获得省电移位寄存器，其将正常状态下的输出信号固定在低电平，而不允许通流通过。
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公开(公告)号：US08269713B2
公开(公告)日：2012-09-18
申请号：US12733117
申请日：2008-05-15
IPC分类号： G09G3/36
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.
摘要翻译： 在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。 通过使用两相时钟信号并且其高电平周期彼此不重叠，复位信号产生电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平 进入高层。 在复位信号为高电平的期间，晶体管T3，T4进行节点的放电，输出信号的下拉。 因此，可以获得省电移位寄存器，其将正常状态下的输出信号固定在低电平，而不允许通流通过。
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公开(公告)号：US08493312B2
公开(公告)日：2013-07-23
申请号：US13571608
申请日：2012-08-10
IPC分类号： G09G3/36
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.
摘要翻译： 在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。 通过使用两相时钟信号并且其高电平周期彼此不重叠，复位信号产生电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平 进入高层。 在复位信号为高电平的期间，晶体管T3，T4进行节点的放电，输出信号的下拉。 因此，可以获得省电移位寄存器，其将正常状态下的输出信号固定在低电平，而不允许通流通过。
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公开(公告)号：US20100141642A1
公开(公告)日：2010-06-10
申请号：US12733119
申请日：2008-05-15
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a shift register which performs discharge of a node and pull-down of an output signal and achieves a small area and low power consumption without using an output signal from a subsequent circuit.
摘要翻译： 在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。 通过使用高电平周期彼此不重叠的两相时钟信号，复位信号生成电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平 高层次。 在复位信号处于高电平的期间，晶体管执行节点的放电和输出信号的下拉。 因此，可以获得执行节点放电和输出信号下拉的移位寄存器，并且在不使用来自后续电路的输出信号的情况下实现小面积和低功耗。
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公开(公告)号：US20120307959A1
公开(公告)日：2012-12-06
申请号：US13571608
申请日：2012-08-10
IPC分类号： G11C19/00
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.
摘要翻译： 在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。 通过使用两相时钟信号并且其高电平周期彼此不重叠，复位信号产生电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平 进入高层。 在复位信号为高电平的期间，晶体管T3，T4进行节点的放电，输出信号的下拉。 因此，可以获得省电移位寄存器，其将正常状态下的输出信号固定在低电平，而不允许通流通过。
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公开(公告)号：US08269714B2
公开(公告)日：2012-09-18
申请号：US12733119
申请日：2008-05-15
IPC分类号： G09G3/36
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a shift register which performs discharge of a node and pull-down of an output signal and achieves a small area and low power consumption without using an output signal from a subsequent circuit.
摘要翻译： 在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。 通过使用高电平周期彼此不重叠的两相时钟信号，复位信号生成电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平 高层次。 在复位信号处于高电平的期间，晶体管执行节点的放电和输出信号的下拉。 因此，可以获得执行节点放电和输出信号下拉的移位寄存器，并且在不使用来自后续电路的输出信号的情况下实现小面积和低功耗。
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公开(公告)号：US08970565B2
公开(公告)日：2015-03-03
申请号：US13378233
申请日：2010-03-18
CPC分类号： G11C19/28 , G09G3/3677 , G09G2310/063
摘要： A stage of the shift register has (i) a set-reset type flip-flop which receives an initialization signal and (ii) a signal generating circuit which receives a simultaneous selection signal and which generates an output signal by use of an output of the flip-flop. In at least one example embodiment, the output of the flip-flop becomes inactive regardless of whether a setting signal and a resetting signal are active or inactive, as long as the initialization signal is active. The initialization signal becomes active before the end of the simultaneous selection, and then becomes inactive after the end of the simultaneous selection. This makes it possible to stabilize operation of the shift register after the end of simultaneous selection of a plurality of signal lines carried out by the display driving circuit at a predetermined timing.
摘要翻译： 移位寄存器的一级具有（i）接收初始化信号的设置复位型触发器，以及（ii）接收同时选择信号并且通过使用输出信号产生输出信号的信号发生电路 拖鞋。 在至少一个示例性实施例中，只要初始化信号有效，触发器的输出就会变得无效，而不管设置信号和复位信号是有效还是无效。 初始化信号在同时选择结束之前变为有效，然后在同时选择结束后变为无效。 这使得可以在预定定时同时选择由显示驱动电路执行的多条信号线结束之后稳定移位寄存器的操作。
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公开(公告)号：US20120200549A1
公开(公告)日：2012-08-09
申请号：US13395518
申请日：2010-04-23
CPC分类号： G09G3/3659 , G09G2300/0842 , G09G2300/0861 , G09G2320/0219 , G09G2330/022
摘要： Provided is a display device which can prevent screen noise caused such that a potential of a common electrode is reversed after a memory mode enters from a refresh period to an entire write-in period, and a method for driving the display device. The memory mode includes (i) an entire write-in period in which a potential of the common electrode (COM) is fixed and the display data is written into all the memory circuits (node (PIX)) in each row and (ii) a refresh period in which the display data which has been written during the entire write-in period is refreshed at least once while the common electrode (COM) is driven. In the memory mode, the potential of the common electrode during the entire write-in period being a potential which the common electrode having been driven had at the end of a refresh period preceding the entire write-in period.
摘要翻译： 提供一种显示装置，其可以防止在从刷新周期进入整个写入周期之后引起公共电极的电位反转的屏幕噪声，以及用于驱动显示装置的方法。 存储模式包括：（i）公共电极（COM）的电位固定并将显示数据写入到每行的所有存储电路（节点（PIX））中的整个写入周期，以及（ii） 在驱动公共电极（COM）的过程中至少刷新一次整个写入周期期间已写入的显示数据的刷新周期。 在存储模式中，公共电极在整个写入周期期间的电位是已经被驱动的公共电极在整个写入周期之前的刷新周期结束时的电位。
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公开(公告)号：US08223112B2
公开(公告)日：2012-07-17
申请号：US12734234
申请日：2008-08-18
CPC分类号： G11C19/28 , G09G3/20 , G09G3/3266 , G09G3/3275 , G09G3/3648 , G09G3/3674 , G09G3/3677 , G09G3/3685 , G09G3/3688 , G09G2300/0426 , G09G2310/0245 , G09G2310/0267 , G09G2310/0275 , G09G2310/0286 , G09G2310/0291
摘要： At least one embodiment of the present invention is directed to, even when external noise is applied to a shift register during all-on operation, preventing through-current from flowing in unit circuits and also to prevent increase in load on all-on control signal lines. When a high-level all-on control signal is provided to a unit circuit of a shift register, a transistor T3 is brought into off-state, so that a transistor T2 cannot output an on-voltage to a first output terminal. However, a transistor T24 is brought into on-state, so that the first output terminal outputs an on-voltage to the exterior. On the other hand, a transistor T32 is brought into on-state, so that a second output terminal outputs an off-voltage to a unit circuit 11 in the next stage. At this time, the transistor T3 is kept in off-state, so that no through-current flows to the transistors T24 and T3.
摘要翻译： 本发明的至少一个实施例涉及即使当在全导通操作期间外部噪声被施加到移位寄存器时，也可以防止在单位电路中流过电流，并且还防止全通控制信号的负载增加 线条。 当向移位寄存器的单元电路提供高电平全通控制信号时，晶体管T3进入截止状态，晶体管T2不能向第一输出端子输出导通电压。 然而，晶体管T24进入导通状态，使得第一输出端子向外部输出导通电压。 另一方面，晶体管T32进入导通状态，使得第二输出端在下一级向单元电路11输出截止电压。 此时，晶体管T3保持截止状态，使得没有贯通电流流向晶体管T24和T3。
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10.发明申请MEMORY DEVICE, DISPLAY DEVICE EQUIPPED WITH MEMORY DEVICE, DRIVE METHOD FOR MEMORY DEVICE, AND DRIVE METHOD FOR DISPLAY DEVICE 有权存储装置，具有存储装置的显示装置，用于存储装置的驱动方法和用于显示装置的驱动方法公开(公告)号：US20120169753A1
公开(公告)日：2012-07-05
申请号：US13496027
申请日：2010-04-23
CPC分类号： G09G3/3659 , G09G2300/0417 , G09G2300/0823 , G09G2300/0842 , G09G2300/0861 , G09G2300/088 , G09G2330/022 , G11C11/405
摘要： A memory device is provided which includes a memory circuit that allows a circuit which carries out a refresh operation to suitably carry out an original operation of the circuit even if an off-leakage current occurs in a transfer element used in a transfer section. A memory cell includes a switching circuit, a first retaining section, a transfer section, a second retaining section, a first control section, and a voltage supply, and the first control section is controlled to be in (i) a state in which the first control section carries out a first operation in which the first control section is in an active state or a non-active state and (ii) a state in which the first control section carries out a second operation.
摘要翻译： 提供了一种存储器件，其包括一个存储器电路，即使在转印部件中使用的转印元件中出现泄漏电流，允许进行刷新操作的电路适当地执行电路的原始操作。 存储单元包括开关电路，第一保持部分，转移部分，第二保持部分，第一控制部分和电压源，并且第一控制部分被控制为处于（i） 第一控制部分执行第一操作，其中第一控制部分处于活动状态或非活动状态，以及（ii）第一控制部分执行第二操作的状态。
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