Load circuit supply voltage control
    41.
    发明申请
    Load circuit supply voltage control 有权
    负载电路电源电压控制

    公开(公告)号:US20070262754A1

    公开(公告)日:2007-11-15

    申请号:US11432815

    申请日:2006-05-11

    申请人: Edward Burton

    发明人: Edward Burton

    IPC分类号: G05F1/70

    摘要: For one disclosed embodiment, an apparatus comprises a load circuit having one or more memory devices, one or more temperature sensors to sense one or more temperatures for the load circuit, and supply voltage control circuitry to control supply voltage to be applied to the load circuit. The supply voltage control circuitry may vary the supply voltage based at least in part on one or more sensed temperatures when the load circuit is in an inactive state and may help retain one or more signals by one or more memory devices of the load circuit as the supply voltage is varied. Other embodiments are also disclosed.

    摘要翻译: 对于一个公开的实施例,一种装置包括具有一个或多个存储器装置的负载电路,用于感测负载电路的一个或多个温度的一个或多个温度传感器,以及供应电压控制电路以控制施加到负载电路的电源电压 。 电源电压控制电路可以在负载电路处于非活动状态时至少部分地基于一个或多个感测到的温度改变电源电压,并且可以有助于通过负载电路的一个或多个存储器件将一个或多个信号保持为 电源电压变化。 还公开了其他实施例。

    Mechanism for adaptively adjusting a direct current loadline in a multi-core processor
    42.
    发明申请
    Mechanism for adaptively adjusting a direct current loadline in a multi-core processor 有权
    在多核处理器中自适应调整直流负载线的机制

    公开(公告)号:US20070260899A1

    公开(公告)日:2007-11-08

    申请号:US11416535

    申请日:2006-05-03

    申请人: Edward Burton

    发明人: Edward Burton

    IPC分类号: G06F1/00

    CPC分类号: G06F1/26

    摘要: A central processing unit (CPU) is disclosed. The CPU includes two or more processing cores and a power control unit to regulate voltage applied to the CPU based upon the number of processing cores that are active.

    摘要翻译: 公开了一种中央处理单元(CPU)。 CPU包括两个或多个处理核心和功率控制单元,用于根据活动的处理核心的数量来调节施加到CPU的电压。

    Power switches having positive-channel high dielectric constant insulated gate field effect transistors
    43.
    发明申请
    Power switches having positive-channel high dielectric constant insulated gate field effect transistors 有权
    具有正通道高介电常数绝缘栅场效应晶体管的电源开关

    公开(公告)号:US20070236850A1

    公开(公告)日:2007-10-11

    申请号:US11394810

    申请日:2006-03-31

    IPC分类号: H02H3/22

    CPC分类号: H01L27/088

    摘要: Power switch units for microelectronic devices are disclosed. In one aspect, a microelectronic device may include a functional circuit, and a power switch unit to switch power to the functional circuit on and off. The power switch unit may include a large number of transistors coupled together. The transistors may include predominantly positive-channel, insulated gate field effect transistors, which have a gate dielectric that includes a high dielectric constant material. Power switch units having such transistors may tend to have low power consumption. In an aspect, an overdrive voltage may be applied to the gates of such transistors to further reduce power consumption. Methods of overdriving such transistors and systems including such power switch units are also disclosed.

    摘要翻译: 公开了用于微电子器件的功率开关单元。 一方面,微电子器件可以包括功能电路,以及电源开关单元,用于将功率电路接通和断开。 电源开关单元可以包括耦合在一起的大量晶体管。 晶体管可以包括主要为正沟道绝缘栅场效应晶体管,其具有包括高介电常数材料的栅极电介质。 具有这种晶体管的功率开关单元倾向于具有低功耗。 在一方面,可以将过驱动电压施加到这种晶体管的栅极,以进一步降低功耗。 还公开了过载驱动这种晶体管和包括这种功率开关单元的系统的方法。

    Method and apparatus to lower operating voltages for memory arrays using error correcting codes
    44.
    发明申请
    Method and apparatus to lower operating voltages for memory arrays using error correcting codes 有权
    使用纠错码降低存储器阵列的工作电压的方法和装置

    公开(公告)号:US20070022360A1

    公开(公告)日:2007-01-25

    申请号:US11174003

    申请日:2005-06-30

    IPC分类号: G11C29/00

    CPC分类号: G11C11/417

    摘要: A method comprising running an error correction code on data and storing the data and the result of the error correction code in memory, running an error correction code on the data when it is read from the memory, comparing the results of the error correction codes on the data from before and after the memory, correcting errors when the comparator determines a difference in the results of the error correction codes and lowering the operating voltage of the memory array while using the error correction.

    摘要翻译: 一种方法,包括在数据上运行纠错码并将数据和纠错码的结果存储在存储器中,当从存储器读取数据时对数据进行纠错码,将纠错码的结果与 来自存储器之前和之后的数据,当比较器确定误差校正码的结果的差异并且在使用纠错时降低存储器阵列的工作电压时校正错误。