公开(公告)号：US20070022360A1

公开(公告)日：2007-01-25

申请号：US11174003

申请日：2005-06-30

申请人： Nivruti Rai ,  Anshumali Kumar ,  Edward Burton ,  Sunit Tyagi ,  Jeffrey Miller

发明人： Nivruti Rai ,  Anshumali Kumar ,  Edward Burton ,  Sunit Tyagi ,  Jeffrey Miller

IPC分类号： G11C29/00

CPC分类号： G11C11/417

摘要： A method comprising running an error correction code on data and storing the data and the result of the error correction code in memory, running an error correction code on the data when it is read from the memory, comparing the results of the error correction codes on the data from before and after the memory, correcting errors when the comparator determines a difference in the results of the error correction codes and lowering the operating voltage of the memory array while using the error correction.

摘要翻译： 一种方法，包括在数据上运行纠错码并将数据和纠错码的结果存储在存储器中，当从存储器读取数据时对数据进行纠错码，将纠错码的结果与 来自存储器之前和之后的数据，当比较器确定误差校正码的结果的差异并且在使用纠错时降低存储器阵列的工作电压时校正错误。

公开(公告)号：US07581154B2

公开(公告)日：2009-08-25

申请号：US11174003

申请日：2005-06-30

申请人： Nivruti Rai ,  Anshumali Kumar ,  Edward Burton ,  Sunit Tyagi ,  Jeffrey L. Miller

发明人： Nivruti Rai ,  Anshumali Kumar ,  Edward Burton ,  Sunit Tyagi ,  Jeffrey L. Miller

IPC分类号： G11C29/00

CPC分类号： G11C11/417

摘要： A method comprising running an error correction code on data and storing the data and the result of the error correction code in memory, running an error correction code on the data when it is read from the memory, comparing the results of the error correction codes on the data from before and after the memory, correcting errors when the comparator determines a difference in the results of the error correction codes and lowering the operating voltage of the memory array while using the error correction.

摘要翻译： 一种方法，包括在数据上运行纠错码并将数据和纠错码的结果存储在存储器中，当从存储器读取数据时对数据进行纠错码，将纠错码的结果与 来自存储器之前和之后的数据，当比较器确定误差校正码的结果的差异并且在使用纠错时降低存储器阵列的工作电压时校正错误。

公开(公告)号：US20070145495A1

公开(公告)日：2007-06-28

申请号：US11319815

申请日：2005-12-27

申请人： Giuseppe Curello ,  Sivakumar Mudanai ,  Nick Lindert ,  Leonard Pipes ,  M. Shaheed ,  Sunit Tyagi

发明人： Giuseppe Curello ,  Sivakumar Mudanai ,  Nick Lindert ,  Leonard Pipes ,  M. Shaheed ,  Sunit Tyagi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823481 ,  H01L21/823412

摘要： A method including forming a transistor structure structure comprising a gate electrode over an active region of a substrate, the active region defined by a trench isolation structure and changing a performance of a narrow width transistor with respect to a wide width transistor by introducing a dopant into the active region adjacent an interface defined by the trench isolation structure and the gate electrode. A structure including a gate electrode formed on a substrate, an active region adjacent an interface defined by a trench isolation structure and a gate electrode and an implant within the active region to change a performance of a transistor.

摘要翻译： 一种包括在衬底的有源区上形成包括栅电极的晶体管结构结构的方法，所述有源区由沟槽隔离结构限定，并且通过将掺杂剂引入到宽宽度晶体管中来改变窄宽晶体管的性能 邻接由沟槽隔离结构和栅电极限定的界面的有源区。 一种结构，包括形成在衬底上的栅电极，与由沟槽隔离结构限定的界面相邻的有源区和栅电极以及有源区内的注入以改变晶体管的性能。

公开(公告)号：US20060145273A1

公开(公告)日：2006-07-06

申请号：US11031843

申请日：2005-01-06

申请人： Giuseppe Curello ,  Bernhard Sell ,  Sunit Tyagi ,  Chris Auth

发明人： Giuseppe Curello ,  Bernhard Sell ,  Sunit Tyagi ,  Chris Auth

IPC分类号： H01L29/94

CPC分类号： H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7842

摘要： Embodiments of the invention provide a transistor with stepped source and drain regions. The stepped regions may provide significant strain in a channel region while minimizing current leakage. The stepped regions may be formed by forming two recesses in a substrate to result in a stepped recess, and forming the source/drain regions in the recesses.

摘要翻译： 本发明的实施例提供了具有阶梯式源极和漏极区域的晶体管。 台阶区域可以在通道区域中提供显着的应变，同时最小化电流泄漏。 可以通过在基板中形成两个凹槽来形成阶梯状区域，以形成阶梯状凹陷，并且在凹部中形成源极/漏极区域。

公开(公告)号：US06384457B2

公开(公告)日：2002-05-07

申请号：US09304601

申请日：1999-05-03

申请人： Sunit Tyagi ,  Shahriar S. Ahmed

发明人： Sunit Tyagi ,  Shahriar S. Ahmed

IPC分类号： H01L2976

CPC分类号： H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

摘要： Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are disclosed. One MOSFET includes, a substrate having a well of a first conductivity type. The MOSFET also includes source and drain regions, of a second conductivity type, formed in the well arranged apart from each other. Moreover, the MOSFET includes a first region, of a second conductivity type, formed in the well near the drain region. The first region has a low doping. Furthermore, the MOSFET includes a second region of a second conductivity type, formed near the source region. The second region has a doping substantially higher than the doping of the first region. A second MOSFET includes a substrate having a well of a first conductivity type and source and drain regions, of a second conductivity type, formed in the well apart from each other. Moreover, the MOSFET includes a drain extension region of the second conductivity type, formed in the well near the drain region. Furthermore, the MOSFET includes a source extension region, of the second conductivity type, formed in the well near the source region. The source extension region is doped more heavily than the drain extension region. The source extension region extends deeper in the well than the drain extension region.

摘要翻译： 公开了金属氧化物半导体场效应晶体管（MOSFET）。 一个MOSFET包括具有第一导电类型的阱的衬底。 MOSFET还包括第二导电类型的源极和漏极区域，其形成在彼此分开布置的阱中。 此外，MOSFET包括形成在漏区附近的阱中的第二导电类型的第一区域。 第一个区域掺杂低。 此外，MOSFET包括在源极区附近形成的第二导电类型的第二区域。 第二区域具有比第一区域的掺杂显着更高的掺杂。 第二MOSFET包括具有第一导电类型的阱以及形成在彼此远离的第二导电类型的源极和漏极区的衬底。 此外，MOSFET包括形成在漏极区附近的阱中的第二导电类型的漏极延伸区域。 此外，MOSFET包括形成在源区附近的阱中的第二导电类型的源极延伸区域。 源极延伸区域比漏极延伸区域更重掺杂。 源极延伸区域在阱中比漏极延伸区域更深。

公开(公告)号：US06177705B1

公开(公告)日：2001-01-23

申请号：US09374057

申请日：1999-08-12

申请人： Sunit Tyagi ,  Shahriar S. Ahmed

发明人： Sunit Tyagi ,  Shahriar S. Ahmed

IPC分类号： H01L2976

CPC分类号： H01L29/7393

摘要： An improved MOS transistor and method for making it are described. The MOS transistor's source and drain have a first conductivity type and are separated from each other by a first region having a second conductivity type opposite to the first conductivity type. A second region, also having the second conductivity type, is formed adjacent to the drain and is separated from the first region by the drain.

摘要翻译： 描述了一种改进的MOS晶体管及其制造方法。 MOS晶体管的源极和漏极具有第一导电类型，并且通过具有与第一导电类型相反的第二导电类型的第一区域彼此分离。 还具有第二导电类型的第二区域邻近漏极形成，并且通过漏极与第一区域分离。

公开(公告)号：US07888710B2

公开(公告)日：2011-02-15

申请号：US11874129

申请日：2007-10-17

申请人： Mark Armstrong ,  Gerhard Schrom ,  Sunit Tyagi ,  Paul A. Packan ,  Kelin J. Kuhn ,  Scott Thompson

发明人： Mark Armstrong ,  Gerhard Schrom ,  Sunit Tyagi ,  Paul A. Packan ,  Kelin J. Kuhn ,  Scott Thompson

IPC分类号： H01L27/148

CPC分类号： H01L27/1446 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/045 ,  H01L29/7843 ,  H01L29/7846

摘要： Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the direction. Additionally, longitudinal tensile stress is applied to the channels.

摘要翻译： 互补金属氧化物半导体晶体管形成在硅衬底上。 基板具有{100}晶体取向。 晶体管形成在衬底上，使得电流在晶体管的沟道中流动平行于<100>方向。 此外，纵向拉伸应力施加到通道。

公开(公告)号：US07560780B2

公开(公告)日：2009-07-14

申请号：US11298095

申请日：2005-12-08

申请人： Giuseppe Curello ,  Ian R. Post ,  Chia-Hong Jan ,  Sunit Tyagi ,  Mark Bohr

发明人： Giuseppe Curello ,  Ian R. Post ,  Chia-Hong Jan ,  Sunit Tyagi ,  Mark Bohr

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L21/823481 ,  H01L21/26506 ,  H01L21/823418 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833 ,  H01L29/7834

摘要： A semiconductor device and method for its fabrication are described. An active region spacer may be formed on a top surface of an isolation region and adjacent to a sidewall of an active region. In one embodiment, the active region spacer may suppress the formation of metal pipes in the active region.

摘要翻译： 对半导体装置及其制造方法进行说明。 有源区隔离物可以形成在隔离区的顶表面上并且邻近有源区的侧壁。 在一个实施例中，有源区间隔物可以抑制活性区域中的金属管的形成。

公开(公告)号：US07473591B2

公开(公告)日：2009-01-06

申请号：US11292428

申请日：2005-12-01

申请人： Stephen M. Cea ,  Ravindra Soman ,  Ramune Nagisetty ,  Sunit Tyagi ,  Sanjay Natarajan

发明人： Stephen M. Cea ,  Ravindra Soman ,  Ramune Nagisetty ,  Sunit Tyagi ,  Sanjay Natarajan

IPC分类号： H01L21/00

CPC分类号： H01L29/66636 ,  H01L29/1054 ,  H01L29/7842

摘要： Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is formed, a relaxed layer is formed on the strain-inducing layer, a portion of the strain-inducing layer is removed, which allows the strain-inducing layer to relax and strain the relaxed layer.

摘要翻译： 用于在器件的沟道区域中形成应变硅层的各种方法以及根据所公开的方法构造的器件。 在一个实施例中，形成应变诱导层，在应变诱导层上形成松弛层，去除应变诱导层的一部分，这使得应变诱导层松弛并使应变放松层。

公开(公告)号：US06249025B1

公开(公告)日：2001-06-19

申请号：US08998257

申请日：1997-12-29

申请人： Sunit Tyagi

发明人： Sunit Tyagi

IPC分类号： H01L2976

CPC分类号： H01L21/76237 ,  H01L21/823892

摘要： The present invention is a semiconductor device having and a method for forming wells by growing an epitaxial silicon layer wherein the epitaxial silicon layer has at least three silicon sublayers. The first sublayer is highly doped, the second sublayer is less doped, and the third sublayer is also highly doped. The use of the epitaxially grown wells allows for the placement of high dopant concentrations in regions of the well where electrical isolation is an issue and the placement of lower doped concentrations in regions of the well where electrical isolation is not as great an issue in order to help reduce the problem of parasitic capacitance.