公开(公告)号：US6114878A

公开(公告)日：2000-09-05

申请号：US023639

申请日：1998-02-13

申请人： Daniel R. Loughmiller ,  Stephen R. Porter

发明人： Daniel R. Loughmiller ,  Stephen R. Porter

IPC分类号： H03K19/173 ,  H03K19/00

CPC分类号： H03K19/1732 ,  H03K19/1731 ,  H01L2224/05554 ,  H01L2224/48247 ,  H01L2224/49171

摘要： A circuit is provided to isolate a contact pad from a logic circuit of a die once the contact pad is no longer needed. This circuit can take many forms including a CMOS multiplexer controlled by a fuse or anti-fuse, an NMOS or PMOS pass gate controlled by a fuse or anti-fuse, or even a fusible link which is severed to effect isolation. Additionally, a circuit is provided that switchably isolates one of two contact pads from a logic circuit.

摘要翻译： 一旦不再需要接触垫，就提供一个电路来隔离接触垫与芯片的逻辑电路。 该电路可以采用许多形式，包括由熔丝或反熔丝控制的CMOS多路复用器，由保险丝或反熔丝控制的NMOS或PMOS通孔，或甚至被切断以实现隔离的可熔链路。 此外，提供了一种电路，其可切换地将两个接触焊盘之一与逻辑电路隔离。

公开(公告)号：US5304506A

公开(公告)日：1994-04-19

申请号：US29088

申请日：1993-03-10

申请人： Stephen R. Porter ,  Navjot Chhabra

发明人： Stephen R. Porter ,  Navjot Chhabra

IPC分类号： H01L21/02 ,  H01L21/70

CPC分类号： H01L28/40

摘要： The present invention discloses an on chip decoupling capacitor structure having a first decoupling capacitor with one electrode formed in the conductively doped silicon substrate and a second electrode made of conductively doped polysilicon. The second electrode is a common electrode to a second decoupling capacitor overlying and thereby coupled in parallel to said first decoupling capacitor. The second capacitor's first electrode is the common electrode and its second electrode is made of conductively doped polysilicon. The electrodes made of the conductively doped polysilicon may be further enhanced by forming a silicided material, such as tungsten silicide, thereon. The decoupling capacitors' dielectric can be formed from high dielectric constant materials, such as TEOS, oxide, nitride or any combination thereof. The second decoupling capacitor could be fabricated over field oxide and used as a single capacitor having a first and second conductively doped polysilicon electrodes (either silicided or non-silicided) with a capacitor dielectric sandwiched in between.

摘要翻译： 本发明公开了一种片上去耦电容器结构，其具有在导电掺杂硅衬底中形成的一个电极的第一去耦电容器和由导电掺杂多晶硅制成的第二电极。 第二电极是与第一去耦电容器并联并由此并联到第一去耦电容器的第二去耦电容器的公共电极。 第二电容器的第一电极是公共电极，其第二电极由导电掺杂的多晶硅制成。 由导电掺杂多晶硅制成的电极可以通过在其上形成诸如硅化钨的硅化物材料进一步增强。 去耦电容器的电介质可以由高介电常数材料形成，例如TEOS，氧化物，氮化物或其任何组合。 第二去耦电容器可以在场氧化物上制造，并且用作具有第一和第二导电掺杂多晶硅电极（硅化或非硅化）的单个电容器，其间夹有电容器电介质。

公开(公告)号：US5297087A

公开(公告)日：1994-03-22

申请号：US54902

申请日：1993-04-29

申请人： Stephen R. Porter

发明人： Stephen R. Porter

IPC分类号： G11C8/12 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/50 ,  G11C8/12 ,  G11C11/401

摘要： A semiconductor memory device includes a plurality of row lines, a plurality of column lines, and a common storage cell plate. The memory device also includes a cell plate generator which produces a reference voltage. The reference voltage is connected to the common storage cell plate. A row decoder connects a row line voltage to selected individual row lines. A stress mode detection circuit receives a row line stress voltage and generates a stress mode signal in response. The row decoder is responsive to the stress mode signal to simultaneously bias all of the row lines to the row line stress voltage. At least one equilibrate circuit is also connected to receive the stress mode signal and is responsive to the stress mode signal to bias the column lines to the reference voltage. The memory device is furthermore responsive to the stress mode signal to ground the reference voltage. The circuits described create a voltage stress differential between the column lines, the row lines, and the common storage cell plate. This voltage stress differential is greater than any voltage differential occurring between the row lines, the column lines, and the storage cell plate during normal memory access operations. The voltage stress differential is maintained for a relatively long period to induce failure of marginally defective dielectric layers within the semiconductor memory device.

摘要翻译： 半导体存储器件包括多条行线，多条列线和公共存储单元板。 存储器件还包括产生参考电压的单元板发生器。 参考电压连接到公共存储单元板。 行解码器将行线电压连接到所选择的各行行。 应力模式检测电路接收行线应力电压并产生应力模式信号。 行解码器响应于应力模式信号，以将所有行线同时偏置到行线应力电压。 还连接至少一个平衡电路以接收应力模式信号，并且响应于应力模式信号以将列线偏置到参考电压。 存储器件还响应于应力模式信号将参考电压接地。 所描述的电路在列线，行线和公共存储单元板之间产生电压应力差。 该电压应力差异大于正常存储器访问操作期间在行线，列线和存储单元板之间发生的任何电压差。 电压应力差异保持相对长的时间段以引起半导体存储器件内的边缘损坏的电介质层的失效。