DIE TESTING USING TOP SURFACE TEST PADS
    41.
    发明申请

    公开(公告)号:US20200278389A1

    公开(公告)日:2020-09-03

    申请号:US16875628

    申请日:2020-05-15

    Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

    TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT

    公开(公告)号:US20200217890A1

    公开(公告)日:2020-07-09

    申请号:US16825434

    申请日:2020-03-20

    Inventor: Lee D. Whetsel

    Abstract: The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.

    SHADOW ACCESS PORT METHOD AND APPARATUS
    44.
    发明申请

    公开(公告)号:US20200217889A1

    公开(公告)日:2020-07-09

    申请号:US16824371

    申请日:2020-03-19

    Inventor: Lee D. Whetsel

    Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.

    TWO PIN SERIAL BUS COMMUNICATION INTERFACE AND PROCESS

    公开(公告)号:US20200090711A1

    公开(公告)日:2020-03-19

    申请号:US16689691

    申请日:2019-11-20

    Inventor: Lee D. Whetsel

    Abstract: A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design.

    Tap, counter storing value of serial access by communication circuitry

    公开(公告)号:US10557887B2

    公开(公告)日:2020-02-11

    申请号:US16290329

    申请日:2019-03-01

    Inventor: Lee D. Whetsel

    Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

    Stack die gating having test control input, output, and enable

    公开(公告)号:US10539606B2

    公开(公告)日:2020-01-21

    申请号:US16047263

    申请日:2018-07-27

    Inventor: Lee D. Whetsel

    Abstract: A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals and outputs control signals to the IR and to the DR. During instruction or data scans, the IR or DRs are enabled to input data from TDI and output data to the TDO MX and the top surface TDO signal. The bottom surface TCI inputs may be coupled to the top surface TCO signals via the gating circuit. The top surface TDI signal may be coupled to the bottom surface TDO signal via TDO MX. This allows concatenating or daisy-chaining the IR and DR of a TCP of a lower die with an IR and DR of a TCP of a die stacked on top of the lower die.

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