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    CONFIGURABLE HYSTERESIS MODULE
    42.
    发明公开
    CONFIGURABLE HYSTERESIS MODULE 审中-公开

    公开(公告)号：US20230296724A1

    公开(公告)日：2023-09-21

    申请号：US17700240

    申请日：2022-03-21

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Anil Mani ,  Sandeep Rao

    IPC: G01S7/02 ,  G01S13/82

    CPC classification number: G01S7/023 ,  G01S7/021 ,  G01S13/82

    Abstract: A frequency-modulated continuous wave (FMCW) radar system is presented. The FMCW radar system includes a receiver configured to receive a radar reflection signal. The radar system further includes an interference detection module, which is configured to identify a portion of the radar reflection signal corresponding to the time period during which the radar reflection signal exceeds a threshold. The FMCW radar system further includes a hysteresis module configured to adjust the identified portion of the radar reflection signal based on the portion of the signal and a hysteresis configuration. The FMCW radar system further includes a mitigation module configured to mitigate interference based on the output of the hysteresis module.

    RADAR SYSTEM IMPLEMENTING SEGMENTED CHIRPS AND PHASE COMPENSATION FOR OBJECT MOVEMENT
    43.
    发明申请
    RADAR SYSTEM IMPLEMENTING SEGMENTED CHIRPS AND PHASE COMPENSATION FOR OBJECT MOVEMENT 有权

    公开(公告)号：US20230094118A1

    公开(公告)日：2023-03-30

    申请号：US17486435

    申请日：2021-09-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Karthik Subburaj ,  Sandeep Rao

    IPC: G01S7/35 ,  G01S13/931 ,  G01S13/58

    Abstract: An apparatus comprises processor cores and computer-readable mediums storing machine instructions for the processor cores. When executing the machine instructions, the processor cores obtain received signals for transmitted chirps from a radar sensor circuit. Each transmitted chirp comprises an A chirp segment, a time gap, and a B chirp segment, respectively. The processor cores sample the received signals to obtain sampled data matrices M1(A) for the A chirp segments and M1(B) for the B chirp segments. The processor cores perform a first Fourier transform (FT) on each column of M1(A) and M1(B) to obtain velocity matrices M2(A) and M2(B), respectively. The processor cores apply a phase compensation factor to M2(B) to obtain a phase corrected velocity matrix M2(B′), and concatenate M2(A) and M2(B′) to obtain an aggregate velocity matrix M2(A&B′). The processor cores perform a second FT on each row of M2(A&B′) to obtain a range and velocity matrix M3(A&B′).

    Maximum Measurable Velocity in Frequency Modulated Continuous Wave (FMCW) Radar
    45.
    发明申请
    Maximum Measurable Velocity in Frequency Modulated Continuous Wave (FMCW) Radar 有权

    公开(公告)号：US20220326368A1

    公开(公告)日：2022-10-13

    申请号：US17843069

    申请日：2022-06-17

    Applicant: Texas Instruments Incorporated

    Inventor： Sandeep Rao ,  Karthik Subburaj ,  Sriram Murali ,  Karthik Ramasubramanian

    IPC: G01S13/28 ,  G06F17/14 ,  G01S7/41 ,  G01S13/536 ,  G01S13/931 ,  G01S13/34 ,  G01S7/35

    Abstract: A radar system is provided that includes a radar transceiver integrated circuit (IC) configurable to transmit a first frame of chirps, and another radar transceiver IC configurable to transmit a second frame of chirps at a time delay ΔT, wherein ΔT=Tc/K, K≥2 and Tc is an elapsed time from a start of one chirp in the first frame and the second frame and a start of a next chirp in the first frame and the second frame, wherein the radar system is configured to determine a velocity of an object in a field of view of the radar system based on first digital intermediate frequency signals generated responsive to receiving reflected chirps of the first frame and second digital IF signals generated responsive to receiving reflected chirps of the time delayed second frame, wherein the maximum measurable velocity is increased by a factor of K.

    ON-FIELD PHASE CALIBRATION
    46.
    发明申请
    ON-FIELD PHASE CALIBRATION 有权

    公开(公告)号：US20220196824A1

    公开(公告)日：2022-06-23

    申请号：US17132857

    申请日：2020-12-23

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sandeep Rao ,  Karthik Subburaj

    IPC: G01S13/58 ,  G01S7/40

    Abstract: A radar system is provided and includes a radar transceiver integrated circuit (IC) and a processor coupled to the radar transceiver IC. The radar transceiver IC includes a chirp generator configured to generate a plurality of chirp signals and a phase shifter configured to induce a signal phase shift. The radar transceiver IC is configured to transmit a frame of chirps based on the plurality of chirp signals and generate a plurality of digital signals, each digital signal corresponding to a respective reflection received based on the plurality of chirp signals. The processor is configured to control the phase shifter to induce the signal phase shift in a first subset of chirp signals of the plurality of chirp signals and determine a phase shift induced in the first subset of chirp signals by the phase shifter based on the digital signal.

    Method and apparatus for FMCW radar processing
    47.
    发明授权
    Method and apparatus for FMCW radar processing 有权

    公开(公告)号：US11209522B2

    公开(公告)日：2021-12-28

    申请号：US16107000

    申请日：2018-08-21

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sandeep Rao ,  Karthik Ramasubramanian

    IPC: G01S7/35 ,  G01S13/42 ,  G01S13/89 ,  G01S13/931 ,  G01S13/58

    Abstract: The disclosure provides a radar apparatus. The radar apparatus includes a transmitter that transmits a first chirp. The first chirp is scattered by one or more obstacles to generate a first plurality of scattered signals. A plurality of receivers receives the first plurality of scattered signals. Each receiver of the plurality of receivers generates a digital signal in response to a scattered signal of the first plurality of scattered signals. A processor is coupled to the plurality of receivers and receives the digital signals from the plurality of receivers. The processor performs range FFT (fast fourier transform) and angle FFT on the digital signals received from the plurality of receivers to generate a first matrix of complex samples.

    Protecting Data Memory in a Signal Processing System
    49.
    发明申请
    Protecting Data Memory in a Signal Processing System 有权

    公开(公告)号：US20210248037A1

    公开(公告)日：2021-08-12

    申请号：US17242636

    申请日：2021-04-28

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sandeep Rao ,  Karthik Ramasubramanian ,  Brian Paul Ginsburg

    IPC: G06F11/10 ,  G01S13/42 ,  G01S13/34 ,  G01S13/931 ,  G01S13/58 ,  G01S7/35 ,  G06F3/06

    Abstract: Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.

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