Abstract:
A power semiconductor device having low on-resistance and a high breakdown voltage is disclosed. The power semiconductor device can be a high power MOS transistor or an insulation gate bipolar transistor. The power semiconductor device has unit cells formed in parallel body region strips. A highly-doped drift layer of the same conductivity type as that of a drift region is provided between adjacent body region strips in a unit cell. Both ends of each of the body region strips of the unit cell are connected to a single frame region. This prevents a depletion region of a spherical or cylindrical type from being formed on an edge of the body region, and in so doing, increases a breakdown voltage of the device.
Abstract:
A trench-type insulated gate bipolar transistor in which a channel stop region is partially formed between an n-type high-concentration emitter region and a p-type base region in which a conductive channel is to be formed. The channel stop region is doped with p-type impurities at high concentration. A portion of the emitter region directly contact the base region, and the other portion has the channel stop region disposed between itself and the base region without directly contacting the base region. At the portion where the channel stop region is interposed, an electron current from the emitter region does not flow vertically into a drift region, but horizontally moves to a direct contacts portion between the emitter region and the base region and then vertically flows to the drift region via the conductive channel. The horizontally-flowing electron current within the emitter region causes a voltage drop, thus reducing the voltage difference at the junction between the emitter region and the base region. Therefore, a latch-up phenomenon, in which a parasitic thyristor is turned on, is suppressed.
Abstract:
A Vbb generator having several distributed Vbb generators, which are located respectively adjacent to memory array blocks is disclosed. The distributed Vbb generator is activated during the time when a memory block located adjacent the Vbb generator is accessed for write/read operations. The back bias voltage generator circuit has a first Vbb generator and a second Vbb generator for supplying a back bias voltage to the substrate. The second Vbb generator comprises an oscillator for generating a clock pulse and a plurality of distributed Vbb generators. The distributed Vbb generators include an auxiliary pumping portion including a buffer portion for buffering the clock pulse from the oscillator, a pumping capacitor connected to the output of the buffer portion for pumping a back bias voltage, and a rectifying portion connected to the pumping capacitor for supplying the back bias voltage to the substrate, and a switch for connecting the clock pulse from the oscillator to the auxiliary pumping portion, the clock pulse activating a pumping operation of the auxiliary pumping portion.