利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

24 条记录 (耗时 0.015 秒)

    Method of Fabricating High-Voltage Semiconductor Device
    1.
    发明申请
    Method of Fabricating High-Voltage Semiconductor Device 有权
    制造高压半导体器件的方法

    公开(公告)号：US20110097864A1

    公开(公告)日：2011-04-28

    申请号：US12985093

    申请日：2011-01-05

    申请人： Jae-gil Lee ,  Chang-wook Kim ,  Ho-cheol Jang ,  Chong-man Yun

    发明人： Jae-gil Lee ,  Chang-wook Kim ,  Ho-cheol Jang ,  Chong-man Yun

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a high-voltage semiconductor device includes the following steps: providing a semiconductor layer; forming a plurality of trenches in the semiconductor layer to define a plurality of pillars of a first conductivity type in the semiconductor layer between adjacent trenches, wherein the trenches extend from a top surface of the semiconductor layer toward a bottom surface of the semiconductor layer; forming a charge compensation layer of a second conductivity type over at least sidewalls of each trench to a predetermined thickness thereby forming a groove in each trench; and substantially filling each groove with a charge compensation plug of the first conductivity type.

    摘要翻译： 一种制造高电压半导体器件的方法包括以下步骤：提供半导体层; 在所述半导体层中形成多个沟槽以在相邻沟槽之间的所述半导体层中限定出第一导电类型的多个柱，其中所述沟槽从所述半导体层的顶表面朝向所述半导体层的底表面延伸; 在每个沟槽的至少侧壁上形成第二导电类型的电荷补偿层至预定厚度，从而在每个沟槽中形成凹槽; 并且用第一导电类型的电荷补偿塞基本上填充每个凹槽。

    Power semiconductor device having high breakdown voltage, low on-resistance and small switching loss and method of forming the same
    3.
    发明授权
    Power semiconductor device having high breakdown voltage, low on-resistance and small switching loss and method of forming the same 有权
    具有高击穿电压，低导通电阻和小开关损耗的功率半导体器件及其形成方法

    公开(公告)号：US07276405B2

    公开(公告)日：2007-10-02

    申请号：US11182578

    申请日：2005-07-14

    申请人： Young-chul Choi ,  Tae-hoon Kim ,  Ho-cheol Jang ,  Chong-man Yun

    发明人： Young-chul Choi ,  Tae-hoon Kim ,  Ho-cheol Jang ,  Chong-man Yun

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7802 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/7395

    摘要： In accordance with one embodiment of the present invention, a power semiconductor device includes a first drift region of a first conductivity type extending over a semiconductor substrate. The first drift region has a lower impurity concentration than the semiconductor substrate. A second drift region of the first conductivity type extends over the first drift region, and has a higher impurity concentration than the first drift region. A plurality of stripe-shaped body regions of a second conductivity type are formed in an upper portion of the second drift region. A third region of the first conductivity type is formed in an upper portion of each body region so as to form a channel region in each body region between the third region and the second drift region. A gate electrode laterally extends over but is insulated from: (i) the channel region in each body region, (ii) a surface area of the second drift region between adjacent stripes of body regions, and (iii) a surface portion of each source region.

    摘要翻译： 根据本发明的一个实施例，功率半导体器件包括在半导体衬底上延伸的第一导电类型的第一漂移区。 第一漂移区域具有比半导体衬底更低的杂质浓度。 第一导电类型的第二漂移区域在第一漂移区域上延伸，并且具有比第一漂移区域更高的杂质浓度。 第二导电类型的多个条形体区域形成在第二漂移区域的上部。 第一导电类型的第三区域形成在每个体区的上部，以便在第三区域和第二漂移区域之间的每个体区域中形成沟道区域。 栅电极横向延伸，但与以下绝缘：（i）每个体区中的沟道区，（ii）相邻的体区之间的第二漂移区的表面积，和（iii）每个源的表面部分 地区。

    Power semiconductor device having high breakdown voltage, low on-resistance and small switching loss and method of forming the same
    4.
    发明申请
    Power semiconductor device having high breakdown voltage, low on-resistance and small switching loss and method of forming the same 有权
    具有高击穿电压，低导通电阻和小开关损耗的功率半导体器件及其形成方法

    公开(公告)号：US20050263818A1

    公开(公告)日：2005-12-01

    申请号：US11182578

    申请日：2005-07-14

    申请人： Young-chul Choi ,  Tae-hoon Kim ,  Ho-cheol Jang ,  Chong-man Yun

    发明人： Young-chul Choi ,  Tae-hoon Kim ,  Ho-cheol Jang ,  Chong-man Yun

    IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L29/94

    CPC分类号： H01L29/7802 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/7395

    摘要： In accordance with one embodiment of the present invention, a power semiconductor device includes a first drift region of a first conductivity type extending over a semiconductor substrate. The first drift region has a lower impurity concentration than the semiconductor substrate. A second drift region of the first conductivity type extends over the first drift region, and has a higher impurity concentration than the first drift region. A plurality of stripe-shaped body regions of a second conductivity type are formed in an upper portion of the second drift region. A third region of the first conductivity type is formed in an upper portion of each body region so as to form a channel region in each body region between the third region and the second drift region. A gate electrode laterally extends over but is insulated from: (i) the channel region in each body region, (ii) a surface area of the second drift region between adjacent stripes of body regions, and (iii) a surface portion of each source region.

    摘要翻译： 根据本发明的一个实施例，功率半导体器件包括在半导体衬底上延伸的第一导电类型的第一漂移区。 第一漂移区域具有比半导体衬底更低的杂质浓度。 第一导电类型的第二漂移区域在第一漂移区域上延伸，并且具有比第一漂移区域更高的杂质浓度。 第二导电类型的多个条形体区域形成在第二漂移区域的上部。 第一导电类型的第三区域形成在每个体区的上部，以便在第三区域和第二漂移区域之间的每个体区域中形成沟道区域。 栅电极横向延伸，但与以下绝缘：（i）每个体区中的沟道区，（ii）相邻的体区之间的第二漂移区的表面积，和（iii）每个源的表面部分 地区。

    Sense FET having a selectable sense current ratio and method of manufacturing the same
    5.
    发明授权
    Sense FET having a selectable sense current ratio and method of manufacturing the same 有权
    具有可选感测电流比的感测FET及其制造方法

    公开(公告)号：US06433386B1

    公开(公告)日：2002-08-13

    申请号：US09161116

    申请日：1998-09-25

    申请人： Chong-man Yun ,  Ki-hyun Lee ,  Kwang-yeon Jun

    发明人： Chong-man Yun ,  Ki-hyun Lee ,  Kwang-yeon Jun

    IPC分类号： H01L2976

    CPC分类号： H01L29/41741 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A sense FET is provided that is capable of achieving one of many available sense current ratios after manufacture, and a method of manufacturing the same. The sense FET includes a main cell array of MOSFET cells connected in parallel, and a main pad connected to the sources of the main cells. A plurality of unit sense cells are arranged in arrays, and also optionally in groups corresponding to portions of the arrays. A plurality of sense pads are electrically insulated from each other. Each sense pad is connected to the sources of the unit sense cells of either a complete sense cell array, or of a group corresponding to a portion of an array. Every sense pad is connected either to the sense resistor or to the main pad. When connected to a sense resistor, the corresponding unit cells are used as sense cells. For every different combination of sense pads that are connected to the sense resistor, a different number of unit cells are used as sense cells, and therefore a different sense current ratio is effectuated for the device. Connection to the sense resistor is by a reconfigurable wire bonding process, or by cutting electrically metal thin film fuses that initially connect the sense pads. The fuses can also initially join the sense pads to the main pad. This way the unit cells of unused sense pads can act instead as main cells.

    摘要翻译： 提供了能够在制造后实现许多可用感测电流比之一的感测FET及其制造方法。 感测FET包括并联连接的MOSFET单元的主单元阵列和连接到主单元的源的主焊盘。 多个单元感测单元被布置成阵列，并且还可选地对应于阵列的一部分的组。 多个感测焊盘彼此电绝缘。 每个感测焊盘连接到完整感测单元阵列或对应于阵列的一部分的组的单元感测单元的源。 每个感测焊盘都连接到检测电阻或主焊盘。 当连接到感测电阻器时，相应的单位单元被用作感测单元。 对于连接到感测电阻器的感测焊盘的每个不同组合，使用不同数量的单元电池作为感测单元，因此对器件实现不同的感测电流比。 通过可重构引线接合工艺或通过切割最初连接感应焊盘的电金属薄膜熔丝连接到检测电阻器。 保险丝也可以最初将感应焊盘连接到主焊盘。 这样，未使用的感测焊盘的单位电池可以代替作为主电池。

    Methods of forming insulated-gate semiconductor devices using self-aligned trench sidewall diffusion techniques
    6.
    发明授权
    Methods of forming insulated-gate semiconductor devices using self-aligned trench sidewall diffusion techniques 失效
    使用自对准沟槽侧壁扩散技术形成绝缘栅半导体器件的方法

    公开(公告)号：US5891776A

    公开(公告)日：1999-04-06

    申请号：US645804

    申请日：1996-05-14

    申请人： Min-Koo Han ,  Chong-Man Yun ,  Yearn-Ik Choi

    发明人： Min-Koo Han ,  Chong-Man Yun ,  Yearn-Ik Choi

    IPC分类号： H01L29/78 ,  H01L21/331 ,  H01L29/10 ,  H01L29/417 ,  H01L29/739 ,  H01L21/22

    CPC分类号： H01L29/66325 ,  H01L29/1095 ,  H01L29/6634 ,  H01L29/7396 ,  H01L29/7398 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7809

    摘要： A method of forming an insulated gate semiconductor device includes the steps of patterning an insulated gate electrode on a face of a substrate containing a first conductivity type region and forming a trench at the face using the gate electrode as a mask. Second conductivity type dopants are then deposited onto the bottom and sidewalls of the trench and diffused into the substrate to form a relatively lightly doped first body region. The gate electrode is then used again as a mask during a step of implanting a relatively high dose of second conductivity type dopants at the bottom of the trench. These implanted dopants are then partially diffused laterally and downwardly away from the bottom and sidewalls of the trench. The gate electrode is then used again to deposit first conductivity type dopants onto the sidewalls (and bottom) of the trench. The deposited first conductivity type dopants on the sidewalls and previously partially diffused second conductivity type dopants are then simultaneously diffused into the first body region. During this step, the deposited first conductivity type dopants diffuse laterally away from the sidewalls of trench and underneath the insulated gate electrode into the surrounding first body region to form source regions. The partially diffused second conductivity type dopants also continue to diffuse laterally away from the lowermost portions of the sidewalls of the trench and downward from the bottom of the trench to form a relatively wide second body region underneath the source region(s).

    摘要翻译： 形成绝缘栅半导体器件的方法包括以下步骤：在包含第一导电类型区域的衬底的表面上构图绝缘栅电极，并使用栅电极作为掩模在面上形成沟槽。 然后将第二导电型掺杂剂沉积到沟槽的底部和侧壁上并扩散到衬底中以形成相对轻掺杂的第一体区。 然后在沟槽底部植入相当高剂量的第二导电类型掺杂剂的步骤期间，再次将栅电极用作掩模。 然后，这些注入的掺杂剂从沟槽的底部和侧壁横向和向下部分扩散。 然后再次使用栅电极将第一导电类型的掺杂剂沉积到沟槽的侧壁（和底部）上。 然后，在侧壁上沉积的第一导电类型掺杂剂和先前部分扩散的第二导电类型掺杂剂然后同时扩散到第一体区。 在该步骤期间，沉积的第一导电类型掺杂剂从沟槽的侧壁和绝缘栅电极下方向侧向扩散到周围的第一体区域中以形成源区。 部分扩散的第二导电类型掺杂剂也继续从沟槽的侧壁的最低部分横向扩散，并且从沟槽的底部向下扩散，以在源极区域下方形成相对较宽的第二体区域。

    Method of fabricating high-voltage semiconductor device
    8.
    发明授权
    Method of fabricating high-voltage semiconductor device 有权
    制造高压半导体器件的方法

    公开(公告)号：US08716085B2

    公开(公告)日：2014-05-06

    申请号：US12985093

    申请日：2011-01-05

    申请人： Jae-gil Lee ,  Chang-wook Kim ,  Ho-cheol Jang ,  Chong-man Yun

    发明人： Jae-gil Lee ,  Chang-wook Kim ,  Ho-cheol Jang ,  Chong-man Yun

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a high-voltage semiconductor device includes the following steps: providing a semiconductor layer; forming a plurality of trenches in the semiconductor layer to define a plurality of pillars of a first conductivity type in the semiconductor layer between adjacent trenches, wherein the trenches extend from a top surface of the semiconductor layer toward a bottom surface of the semiconductor layer; forming a charge compensation layer of a second conductivity type over at least sidewalls of each trench to a predetermined thickness thereby forming a groove in each trench; and substantially filling each groove with a charge compensation plug of the first conductivity type.

    摘要翻译： 一种制造高电压半导体器件的方法包括以下步骤：提供半导体层; 在所述半导体层中形成多个沟槽以在相邻沟槽之间的所述半导体层中限定出第一导电类型的多个柱，其中所述沟槽从所述半导体层的顶表面朝向所述半导体层的底表面延伸; 在每个沟槽的至少侧壁上形成第二导电类型的电荷补偿层至预定厚度，从而在每个沟槽中形成凹槽; 并且用第一导电类型的电荷补偿塞基本上填充每个凹槽。

    Power semiconductor device using silicon substrate as field stop layer and method of manufacturing the same
    10.
    发明授权
    Power semiconductor device using silicon substrate as field stop layer and method of manufacturing the same 有权
    使用硅衬底作为场效应层的功率半导体器件及其制造方法

    公开(公告)号：US07645659B2

    公开(公告)日：2010-01-12

    申请号：US11289823

    申请日：2005-11-30

    申请人： Chong-man Yun ,  Kwang-hoon Oh ,  Kyu-hyun Lee ,  Young-chull Kim

    发明人： Chong-man Yun ,  Kwang-hoon Oh ,  Kyu-hyun Lee ,  Young-chull Kim

    IPC分类号： H01L23/58

    CPC分类号： H01L29/7395 ,  H01L29/66333 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are a power semiconductor device using a silicon substrate as a FS layer and a method of manufacturing the same. A semiconductor substrate of a first conductivity type is prepared. An epitaxial layer is grown on one surface of the semiconductor substrate. Here, the epitaxial layer is doped at a concentration lower than that of the semiconductor substrate and is intended to be used as a drift region. A base region of a second conductivity type is formed in a predetermined region of the epitaxial layer. An emitter region of the first conductivity type is formed in a predetermined region of the base region. A gate electrode with a gate insulating layer is formed on the base region between the emitter region and the drift region of the epitaxial layer. A rear surface of the semiconductor substrate is ground to reduce the thickness of the semiconductor substrate, thereby setting an FS region of the first conductivity type. A collector region of the second conductivity type is formed on the ground surface of the semiconductor substrate of the FS region, thereby forming an FS-IGBT.

    摘要翻译： 提供了使用硅衬底作为FS层的功率半导体器件及其制造方法。 制备第一导电类型的半导体衬底。 在半导体衬底的一个表面上生长外延层。 这里，以比半导体衬底低的浓度掺杂外延层，并且旨在用作漂移区域。 在外延层的预定区域中形成第二导电类型的基极区域。 第一导电类型的发射极区域形成在基极区域的预定区域中。 在外延层的发射极区域和漂移区域之间的基极区域上形成具有栅极绝缘层的栅电极。 研磨半导体衬底的后表面以减小半导体衬底的厚度，由此设置第一导电类型的FS区。 在FS区域的半导体衬底的地表面上形成第二导电类型的集电极区域，从而形成FS-IGBT。