公开(公告)号：US06607955B2

公开(公告)日：2003-08-19

申请号：US09825346

申请日：2001-04-04

申请人： Kyu-Hyun Lee

发明人： Kyu-Hyun Lee

IPC分类号： H01L218242

CPC分类号： H01L21/76897 ,  H01L21/32139

摘要： A method of forming self-aligned contacts in a semiconductor device wherein a silicon nitride layer and a polysilicon layer are formed on a gate electrode layer. The polysilicon layer, the silicon nitride layer, and the gate electrode layer are etched to form gate electrode configurations. Sidewall spacers are formed on both sidewalls of the gate electrode configurations. An oxide layer is then deposited on the resulting structure. Selected portions of the oxide layer are etched to form self-aligned contacts that expose the semiconductor substrate. Because the polysilicon has an excellent etch selectivity with respect to the oxide layer, the gate electrode layer can be sufficiently protected during the etching of the oxide layer resulting in a good shoulder margin at the exposed upper edges of the silicon nitride gate mask layer.

摘要翻译： 在半导体器件中形成自对准接触的方法，其中在栅电极层上形成氮化硅层和多晶硅层。 蚀刻多晶硅层，氮化硅层和栅电极层以形成栅电极构造。 侧壁间隔物形成在栅电极构造的两个侧壁上。 然后在所得结构上沉积氧化物层。 蚀刻氧化物层的选定部分以形成露出半导体衬底的自对准接触。 由于多晶硅相对于氧化物层具有优异的蚀刻选择性，所以在蚀刻氧化物层期间可以充分保护栅电极层，从而在氮化硅栅极掩模层的暴露的上边缘处产生良好的肩部边缘。

公开(公告)号：US06337275B1

公开(公告)日：2002-01-08

申请号：US09334669

申请日：1999-06-17

申请人： Chang-Hyun Cho ,  Kyu-Hyun Lee ,  Jae-Goo Lee ,  Sang-Sup Jeong

发明人： Chang-Hyun Cho ,  Kyu-Hyun Lee ,  Jae-Goo Lee ,  Sang-Sup Jeong

IPC分类号： H01L2144

CPC分类号： H01L21/76897 ,  H01L21/76834

摘要： A self aligned contact (SAC) pad in a semiconductor device and a method for forming thereof wherein an SAC opening is formed concurrently with single-layer gate spacers. After formation of the stacked gate pattern having a gate electrode and a capping layer disposed thereon, an insulating layer for gate spacers is deposited thereon. An interlayer insulating layer then is deposited over the insulating layer. The interlayer insulating layer has an etch selectivity with respect to the capping layer and insulating layer. SAC then are opened in the interlayer insulating layer while concurrently forming single-layer gate spacers.

摘要翻译： 半导体器件中的自对准接触（SAC）焊盘及其形成方法，其中SAC开口与单层栅极间隔物同时形成。 在形成具有设置在其上的栅电极和覆盖层的堆叠栅极图案之后，在其上沉积栅极间隔物的绝缘层。 然后在绝缘层上沉积层间绝缘层。 层间绝缘层相对于覆盖层和绝缘层具有蚀刻选择性。 然后在层间绝缘层中打开SAC，同时形成单层栅极间隔物。

公开(公告)号：US06235623B1

公开(公告)日：2001-05-22

申请号：US09184227

申请日：1998-11-02

申请人： Kyu-Hyun Lee

发明人： Kyu-Hyun Lee

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/0334 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuit contact holes may be formed on an integrated circuit substrate, by providing a first conductive pattern on the substrate, a first interlayer insulating film on the first conductive pattern, a second conductive pattern on the first interlayer insulating film and a second interlayer insulating film on the second conductive pattern. A blocking layer pattern is formed on the second interlayer insulating film. The blocking layer pattern overlies, is of the same pattern as, and is as least as wide as the second conductive pattern. The first and second interlayer insulating films are then selectively etched relative to the blocking layer pattern and the second conductive pattern, to form contact holes that expose the first conductive pattern. A photoresist pattern may also be formed on a portion of the blocking layer pattern. Then, the first and second interlayer insulating films are selectively etched relative to the photoresist pattern, the blocking layer pattern and the second conductive pattern, to form contact holes that expose the first conductive pattern. The above-described integrated circuit contact hole forming methods may also be used to form integrated circuit contact holes for integrated circuit memory devices. For integrated circuit memory devices, the first conductive pattern may correspond to pad electrodes, the second conductive pattern may correspond to bit lines, and capacitor contact plugs may be formed in the contact holes.

摘要翻译： 集成电路接触孔可以形成在集成电路基板上，通过在基板上设置第一导电图案，在第一导电图案上设置第一层间绝缘膜，在第一层间绝缘膜上形成第二导电图案，将第二层间绝缘膜 在第二导电图案上。 在第二层间绝缘膜上形成阻挡层图案。 阻挡层图案覆盖，具有与第二导电图案相同的图案，并且至少与第二导电图案一样宽。 然后相对于阻挡层图案和第二导电图案选择性地蚀刻第一和第二层间绝缘膜，以形成露出第一导电图案的接触孔。 也可以在阻挡层图案的一部分上形成光致抗蚀剂图案。 然后，相对于光致抗蚀剂图案，阻挡层图案和第二导电图案选择性地蚀刻第一和第二层间绝缘膜，以形成暴露第一导电图案的接触孔。 上述集成电路接触孔形成方法也可用于形成用于集成电路存储器件的集成电路接触孔。 对于集成电路存储器件，第一导电图案可以对应于焊盘电极，第二导电图案可以对应于位线，并且电容器接触插塞可以形成在接触孔中。

公开(公告)号：US08729675B1

公开(公告)日：2014-05-20

申请号：US13763927

申请日：2013-02-11

申请人： Jay-Bok Choi ,  Kyu-Hyun Lee ,  Mi-Jeong Jang ,  Young-Jin Choi ,  Ju-Young Huh

发明人： Jay-Bok Choi ,  Kyu-Hyun Lee ,  Mi-Jeong Jang ,  Young-Jin Choi ,  Ju-Young Huh

IPC分类号： H01L29/40

CPC分类号： H01L23/49838 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10847 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a plurality of parallel-trenches that are parallel to each other, a plurality of intersect-trenches that are parallel to each other, a plurality of active regions that are confined by the parallel-trenches and the intersect-trenches, a plurality of lower conductive lines that cross the active regions, a plurality of upper conductive lines that are parallel to each other, that cross the lower conductive lines, and that cross over the active regions, and data storage elements connected to the active regions. Each of the parallel-trenches and the intersect-trenches is a straight line. The parallel-trenches cross the upper conductive lines and form a first acute angle with the upper conductive lines. The intersect-trenches cross the parallel-trenches and form a second acute angle with the parallel-trenches.

摘要翻译： 半导体器件包括彼此平行的多个平行沟槽，彼此平行的多个相交沟槽，由平行沟槽和交叉沟槽约束的多个有源区域，一个 穿过有源区的多个下导电线，彼此平行的多个上导线，穿过下导电线，并跨越有源区，以及连接到有源区的数据存储元件。 每个平行沟槽和交叉沟槽都是直线。 平行沟槽穿过上导电线并与上导线形成第一锐角。 交叉沟槽与平行沟槽交叉并与平行沟槽形成第二锐角。

公开(公告)号：US06890841B2

公开(公告)日：2005-05-10

申请号：US10442481

申请日：2003-05-21

申请人： Kyu-hyun Lee ,  Tae-young Chung ,  Chang-hyun Cho ,  Yang-keun Park ,  Sang-bum Kim

发明人： Kyu-hyun Lee ,  Tae-young Chung ,  Chang-hyun Cho ,  Yang-keun Park ,  Sang-bum Kim

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L21/20 ,  H01L29/94

CPC分类号： H01L28/60 ,  H01L21/76895 ,  H01L28/91 ,  Y10S257/908

摘要： An integrated circuit memory device is formed by forming an interlevel insulating layer on a substrate. A plurality of storage node contact holes are formed in the interlayer insulating layer and are arranged in a pattern. A plurality of contact plugs are formed in the plurality of storage node contact holes, respectively. A material layer is formed on the interlevel insulating layer that has a plurality of landing pad holes that expose the plurality of contact plugs, respectively, the plurality of landing pad holes are arranged in a pattern that is offset with respect to the pattern of the storage node contact holes. A plurality of landing pads are formed in the plurality of landing pad holes and are connected to the plurality of contact plugs, respectively. A plurality of storage nodes are formed that are connected to the plurality of landing pads, respectively.

摘要翻译： 通过在衬底上形成层间绝缘层来形成集成电路存储器件。 在层间绝缘层中形成多个存储节点接触孔，并以图案排列。 多个接触插塞分别形成在多个存储节点接触孔中。 在层间绝缘层上形成材料层，其具有分别露出多个接触插塞的多个着陆焊盘孔，多个着陆焊盘孔以相对于存储器的图案偏移的图案布置 节点接触孔。 多个着陆焊盘形成在多个着陆焊盘孔中，分别连接到多个接触插塞。 形成分别连接到多个着陆焊盘的多个存储节点。

公开(公告)号：US06730975B2

公开(公告)日：2004-05-04

申请号：US10207169

申请日：2002-07-30

申请人： Byung-Jun Park ,  Kyu-Hyun Lee

发明人： Byung-Jun Park ,  Kyu-Hyun Lee

IPC分类号： H01L31119

CPC分类号： H01L27/10855 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/10885 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A DRAM device in which a portion of bit lines has enlarged width portions at a portion of a peripheral/core area to be connected with upper layered circuit wiring through metal contacts, includes spacers formed of a layer of material having an etch selectivity with respect to a bit line interlayer insulating layer deposited after said bit lines are formed, and disposed on sides of an upper surface of each said enlarged width portion to protect sides of said enlarged width portions; an interlayer insulating layer and at least a portion of an etch stop layer disposed between said bit lines and transistors of a substrate; and metal contact pads formed along with bit line contact plugs to pass through said interlayer insulating layer and said etch stop layer.

摘要翻译： 一种DRAM器件，其中位线的一部分在通过金属触点与上部分层电路布线连接的外围/核心区域的一部分处具有扩大的宽度部分，包括由相对于 在所述位线形成之后沉积的位线层间绝缘层，并且设置在每个所述扩大宽度部分的上表面的侧面上，以保护所述扩大宽度部分的侧面; 层间绝缘层和设置在基板的所述位线和晶体管之间的蚀刻停止层的至少一部分; 以及与位线接触插塞一起形成的金属接触垫，以穿过所述层间绝缘层和所述蚀刻停止层。

公开(公告)号：US06602773B2

公开(公告)日：2003-08-05

申请号：US09840741

申请日：2001-04-23

申请人： Kyu-Hyun Lee ,  Yoon-Soon Chun

发明人： Kyu-Hyun Lee ,  Yoon-Soon Chun

IPC分类号： H01L213205

CPC分类号： H01L21/76843 ,  H01L21/7684 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of methods of fabricating protected contact plugs include forming an electrically insulating layer having a contact hole therein, on a semiconductor substrate and then forming an electrically conductive lower barrier layer that lines at least an upper portion of a sidewall of the contact hole. This lower barrier layer may comprise titanium nitride (TiN). A step is also performed to form an electrically conductive contact plug that extends in the contact hole, is electrically coupled to the lower barrier layer and protrudes above the electrically insulating layer. The contact plug may comprise tungsten (W). An electrically conductive upper barrier layer is then formed that extends on a protruded upper surface of the contact plug and on a surface of the lower barrier layer. A step may then be performed to pattern the upper barrier layer to define an electrically conductive barrier spacer that extends on a sidewall or end of the lower barrier layer and define an upper barrier layer cap on the protruded upper surface of the contact plug.

摘要翻译： 制造受保护的接触插塞的方法的实施例包括在半导体衬底上形成其中具有接触孔的电绝缘层，然后形成在接触孔的侧壁的至少上部分上的导电下阻挡层。 该下阻挡层可以包括氮化钛（TiN）。 还执行步骤以形成在接触孔中延伸的导电接触插塞，电连接到下阻挡层并突出在电绝缘层上方。 接触塞可以包括钨（W）。 然后形成导电上阻挡层，其在接触插塞的突出的上表面上延伸并且在下阻挡层的表面上延伸。 然后可以执行步骤以图案化上阻挡层以限定在下阻挡层的侧壁或端部上延伸并且在接触插塞的突出的上表面上限定上阻挡层帽的导电阻挡间隔物。

公开(公告)号：US06485743B1

公开(公告)日：2002-11-26

申请号：US09582536

申请日：2000-06-29

申请人： Jae-Young Jung ,  Kye-Hyun Kim ,  Sang-Heon Lee ,  Ji-Woong Hong ,  Jong-Woo Park ,  Kyu-Hyun Lee

发明人： Jae-Young Jung ,  Kye-Hyun Kim ,  Sang-Heon Lee ,  Ji-Woong Hong ,  Jong-Woo Park ,  Kyu-Hyun Lee

IPC分类号： A61K920

CPC分类号： A61K31/496 ,  A61K9/146 ,  A61K9/1635 ,  A61K9/1652

摘要： The present invention relates to a method and composition of an oral preparation of itraconazole, an excellent azole antifungal drug. More particularly, it relates to an oral preparation of itraconazole having improved bioavailability, which is prepared by following steps of: i) dissolving itraconazole and bydrophilic polymer with solvent, ii) spray-drying said mixture, and iii) preparing the solid dispersions for oral preparation. The solid dispersions prepared in this invention may be useful in preparing tablets, granules and other oral dosage forms.

摘要翻译： 本发明涉及伊曲康唑口服制剂的方法和组合物，优良的唑类抗真菌药物。 更具体地说，本发明涉及伊曲康唑具有改善的生物利用度的口服制剂，其通过以下步骤制备：i）用溶剂溶解伊曲康唑和嗜中性聚合物，ii）喷雾干燥所述混合物，和iii）制备用于口服的固体分散体 制备。 本发明制备的固体分散体可用于制备片剂，颗粒剂和其它口服剂型。

公开(公告)号：US06262470B1

公开(公告)日：2001-07-17

申请号：US09369487

申请日：1999-08-05

申请人： Kyu-hyun Lee ,  Tae-hoon Kim

发明人： Kyu-hyun Lee ,  Tae-hoon Kim

IPC分类号： H01L27082

CPC分类号： H01L29/66348 ,  H01L29/7397

摘要： A trench-type insulated gate bipolar transistor in which a channel stop region is partially formed between an n-type high-concentration emitter region and a p-type base region in which a conductive channel is to be formed. The channel stop region is doped with p-type impurities at high concentration. A portion of the emitter region directly contact the base region, and the other portion has the channel stop region disposed between itself and the base region without directly contacting the base region. At the portion where the channel stop region is interposed, an electron current from the emitter region does not flow vertically into a drift region, but horizontally moves to a direct contacts portion between the emitter region and the base region and then vertically flows to the drift region via the conductive channel. The horizontally-flowing electron current within the emitter region causes a voltage drop, thus reducing the voltage difference at the junction between the emitter region and the base region. Therefore, a latch-up phenomenon, in which a parasitic thyristor is turned on, is suppressed.

摘要翻译： 沟槽型绝缘栅双极晶体管，其中沟道阻挡区域部分地形成在要形成导电沟道的n型高浓度发射极区域和p型基极区域之间。 通道停止区以高浓度掺杂p型杂质。 发射极区域的一部分直接接触基极区域，另一部分具有设置在其与基极区域之间的沟道阻挡区域，而不直接接触基极区域。 在插入通道停止区域的部分，来自发射极区域的电子电流不会垂直流入漂移区域，而是水平移动到发射极区域和基极区域之间的直接接触部分，然后垂直地流到漂移区域 区域。 发射极区域内的水平流动的电子电流引起电压降，从而降低发射极区域和基极区域之间的结处的电压差。 因此，抑制了寄生晶闸管导通的闭锁现象。

公开(公告)号：US20140117566A1

公开(公告)日：2014-05-01

申请号：US13763927

申请日：2013-02-11

申请人： Jay-Bok CHOI ,  Kyu-Hyun LEE ,  Mi-Jeong JANG ,  Young-Jin CHOI ,  Ju-Young HUH

发明人： Jay-Bok CHOI ,  Kyu-Hyun LEE ,  Mi-Jeong JANG ,  Young-Jin CHOI ,  Ju-Young HUH

IPC分类号： H01L23/498

CPC分类号： H01L23/49838 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10847 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a plurality of parallel-trenches that are parallel to each other, a plurality of intersect-trenches that are parallel to each other, a plurality of active regions that are confined by the parallel-trenches and the intersect-trenches, a plurality of lower conductive lines that cross the active regions, a plurality of upper conductive lines that are parallel to each other, that cross the lower conductive lines, and that cross over the active regions, and data storage elements connected to the active regions. Each of the parallel-trenches and the intersect-trenches is a straight line. The parallel-trenches cross the upper conductive lines and form a first acute angle with the upper conductive lines. The intersect-trenches cross the parallel-trenches and form a second acute angle with the parallel-trenches.

摘要翻译： 半导体器件包括彼此平行的多个平行沟槽，彼此平行的多个相交沟槽，由平行沟槽和交叉沟槽约束的多个有源区域，一个 穿过有源区的多个下导电线，彼此平行的多个上导线，穿过下导电线，并跨越有源区，以及连接到有源区的数据存储元件。 每个平行沟槽和交叉沟槽都是直线。 平行沟槽穿过上导电线并与上导线形成第一锐角。 交叉沟槽与平行沟槽交叉并与平行沟槽形成第二锐角。