公开(公告)号：US10854729B2

公开(公告)日：2020-12-01

申请号：US16578360

申请日：2019-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsan-Chun Wang ,  Ziwei Fang ,  Chii-Horng Li ,  Tze-Liang Lee ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/265

Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.

公开(公告)号：US10749007B2

公开(公告)日：2020-08-18

申请号：US15920866

申请日：2018-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ricky Wang ,  Chao-Cheng Chen ,  Jr-Jung Lin ,  Chi-Wei Yang

IPC: H01L29/423 ,  H01L21/3213 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

Abstract: Semiconductor device structures comprising a gate structure having different profiles at different portions of the gate structure are provided. In some examples, a semiconductor device includes a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.

公开(公告)号：US20190122888A1

公开(公告)日：2019-04-25

申请号：US16217167

申请日：2018-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Chao Lin ,  Chao-Cheng Chen ,  Chun-Hung Lee ,  Yu-Lung Yang

IPC: H01L21/033 ,  H01L21/3213 ,  H01L21/308 ,  H01L21/311

Abstract: A method includes forming mandrel patterns over a substrate; depositing a spacer layer over the mandrel patterns and onto sidewalls of the mandrel patterns; trimming the spacer layer to reduce a thickness of the spacer layer along a pattern width direction; and etching the spacer layer to expose the mandrel patterns, resulting in a patterned spacer layer on the sidewalls of the mandrel patterns. The trimming of the spacer layer and the etching of the spacer layer are performed in separate processes. After the trimming of the spacer layer and the etching of the spacer layer, the method further includes removing the mandrel patterns.

公开(公告)号：US10157742B2

公开(公告)日：2018-12-18

申请号：US15096541

申请日：2016-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Chao Lin ,  Chao-Cheng Chen ,  Chun-Hung Lee ,  Yu-Lung Yang

IPC: H01L21/302 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3065 ,  H01L21/02

Abstract: An integrated circuit manufacturing method includes forming mandrel patterns over a patterning layer of a substrate; and forming a spacer layer over the patterning layer, over the mandrel patterns, and onto sidewalls of the mandrel patterns. The method further includes trimming the spacer layer using a dry etching technique such that a space between adjacent sidewalls of the spacer layer substantially matches a dimension of the mandrel patterns along a pattern width direction. The method further includes etching the spacer layer to expose the mandrel patterns and the patterning layer, resulting in a patterned spacer layer on the sidewalls of the mandrel patterns. After the trimming of the spacer layer and the etching of the spacer layer, the method further includes removing the mandrel patterns. The method further includes transferring a pattern of the patterned spacer layer to the patterning layer.

公开(公告)号：US09281196B2

公开(公告)日：2016-03-08

申请号：US14175194

申请日：2014-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsan-Chun Wang ,  Ziwei Fang ,  Chii-Horng Li ,  Tze-Liang Lee ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L29/66537 ,  H01L21/26513 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66651

Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.

Abstract translation: 本公开涉及一种形成晶体管器件的方法。 在该方法中，第一和第二阱区形成在半导体衬底内。 第一和第二阱区域分别具有彼此不同的第一和第二蚀刻速率。 将掺杂剂选择性地注入第一阱区以改变第一蚀刻速率以使第一蚀刻速率基本上等于第二蚀刻速率。 蚀刻第一选择性注入的阱区和第二阱区以形成具有相等凹槽深度的沟槽。 进行外延生长工艺以在通道凹槽内形成一个或多个外延层。

公开(公告)号：US20150187927A1

公开(公告)日：2015-07-02

申请号：US14175194

申请日：2014-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsan-Chun Wang ,  Ziwei Fang ,  Chii-Horng Li ,  Tze-Liang Lee ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC: H01L29/78 ,  H01L21/265

CPC classification number: H01L29/66537 ,  H01L21/26513 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66651

Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.

Abstract translation: 本公开涉及一种形成晶体管器件的方法。 在该方法中，第一和第二阱区形成在半导体衬底内。 第一和第二阱区域分别具有彼此不同的第一和第二蚀刻速率。 将掺杂剂选择性地注入第一阱区以改变第一蚀刻速率以使第一蚀刻速率基本上等于第二蚀刻速率。 蚀刻第一选择性注入的阱区和第二阱区以形成具有相等凹槽深度的沟槽。 进行外延生长工艺以在通道凹槽内形成一个或多个外延层。

公开(公告)号：US20220238387A1

公开(公告)日：2022-07-28

申请号：US17658697

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L21/8234 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes depositing a dummy gate dielectric layer over a semiconductor region, depositing a dummy gate electrode layer, and performing a first etching process. An upper portion of the dummy gate electrode layer is etched to form an upper portion of a dummy gate electrode. The method further includes forming a protection layer on sidewalls of the upper portion of the dummy gate electrode, and performing a second etching process. A lower portion of the dummy gate electrode layer is etched to form a lower portion of the dummy gate electrode. A third etching process is then performed to etch the lower portion of the dummy gate electrode using the protection layer as an etching mask. The dummy gate electrode is tapered by the third etching process. The protection layer is removed, and the dummy gate electrode is replaced with a replacement gate electrode.

公开(公告)号：US11309403B2

公开(公告)日：2022-04-19

申请号：US16822609

申请日：2020-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal gate.

公开(公告)号：US20210367058A1

公开(公告)日：2021-11-25

申请号：US17018793

申请日：2020-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66 ,  H01L29/78

Abstract: A method includes forming a dummy gate electrode on a semiconductor region, forming a first gate spacer on a sidewall of the dummy gate electrode, and removing an upper portion of the first gate spacer to form a recess, wherein a lower portion of the first gate spacer remains, filling the recess with a second gate spacer, removing the dummy gate electrode to form a trench, and forming a replacement gate electrode in the trench.

公开(公告)号：US20210134982A1

公开(公告)日：2021-05-06

申请号：US16822609

申请日：2020-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/306 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal gate.