公开(公告)号：US11056568B2

公开(公告)日：2021-07-06

申请号：US16449837

申请日：2019-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Georgios Vellianitis ,  Gerben Doornbos

IPC: H01L29/00 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/775 ,  H01L29/786 ,  B82Y10/00 ,  H01L21/8234 ,  H01L29/10

Abstract: A method is provided. First and second fins are etched to form a first recess over the etched first fin and a second recess over the etched second fin. A first composite fin and a second composite fin are concurrently epitaxially grown respectively in the first recess and the second recess. The first composite fin includes a plurality of nanowire channels and at least one sacrificial layer. The second composite fin includes at least one nanowire channel and at least one sacrificial layer. A number of the plurality of nanowire channels of the first composite fin is greater than a number of the at least one nanowire channel of the second composite fin. A dielectric material is recessed to expose at least a portion of the first composite fin and at least a portion of the second composite fin.

公开(公告)号：US11004958B2

公开(公告)日：2021-05-11

申请号：US16271964

申请日：2019-02-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Blandine Duriez ,  Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Timothy Vasen

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/08 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417

Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a channel region of a semiconductor layer, a source/drain epitaxial layer is formed on opposing sides of the dummy gate structure, a planarization operation is performed on the source/drain epitaxial layer, the planarized source/drain epitaxial layer is patterned, the dummy gate structure is removed to form a gate space, and a metal gate structure is formed in the gate space.

公开(公告)号：US11004789B2

公开(公告)日：2021-05-11

申请号：US16587671

申请日：2019-09-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Gerben Doornbos ,  Marcus Johannes Henricus Van Dal

IPC: H01L29/78 ,  H01L29/66 ,  H01L23/528 ,  H01L23/48 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a substrate, a main circuit disposed over a front surface of the substrate, and a backside power delivery circuit disposed over a back surface of the substrate. The backside power delivery circuit includes a first main power supply wiring for supplying a first voltage, a second main power supply wiring for supplying a second voltage, a first local power supply wiring, and a first switch coupled to the first main power supply wiring and the first local power supply wiring. The first main power supply wiring, the second main power supply wiring and the first local power supply wiring are embedded in a first back side insulating layer disposed over the back surface of the substrate. The first local power supply wiring is coupled to the main circuit via a first through-silicon via (TSV) passing through the substrate for supplying the first voltage.

公开(公告)号：US10950546B1

公开(公告)日：2021-03-16

申请号：US16573459

申请日：2019-09-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Gerben Doornbos

IPC: H01L23/528 ,  H01L27/118 ,  H01L27/092 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/48 ,  H01L23/522 ,  H01L27/12 ,  H01L21/84 ,  H01L23/535 ,  H01L21/762

Abstract: A semiconductor device includes a substrate, a front side circuit disposed over a front surface of the substrate, and a backside power delivery circuit disposed over a back surface and including a back side power supply wiring coupled to a first potential. The front side circuit includes semiconductor fins and a first front side insulating layer covering bottom portions of the semiconductor fins, a plurality of buried power supply wirings embedded in the first front side insulating layer, the plurality of buried power supply wirings including a first buried power supply wiring and a second buried power supply wiring, and a power switch configured to electrically connect and disconnect the first buried power supply wiring and the second buried power supply wiring. The second buried power supply wiring is connected to the back side power supply wiring by a first through-silicon via passing through the substrate.

公开(公告)号：US10756174B2

公开(公告)日：2020-08-25

申请号：US15613339

申请日：2017-06-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark Van Dal ,  Gerben Doornbos ,  Chung-Te Lin

IPC: H01L21/82 ,  H01L27/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/822 ,  H01L29/40 ,  H01L29/08 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775 ,  H01L21/02

Abstract: A semiconductor device includes a substrate, a gate structure, at least one nanowire, at least one epitaxy structure, and at least one source/drain spacer. The gate structure is disposed on the substrate. The nanowire extends through the gate structure. The epitaxy structure is disposed on the substrate and is in contact with the nanowire. The source/drain spacer is disposed between the epitaxy structure and the gate structure and is embedded in the epitaxy structure.

公开(公告)号：US20200006542A1

公开(公告)日：2020-01-02

申请号：US16194140

申请日：2018-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Gerben Doornbos ,  Matthias Passlack

IPC: H01L29/775 ,  H01L29/205 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.

公开(公告)号：US20190131180A1

公开(公告)日：2019-05-02

申请号：US15798227

申请日：2017-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark VAN DAL ,  Gerben Doornbos

IPC: H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a bottom portion, an intermediate portion disposed over the bottom portion and an upper portion disposed over the intermediate portion is formed. The intermediate portion is removed at a source/drain region of the fin structure, thereby forming a space between the bottom portion and the upper portion. An insulating layer is formed in the space. A source/drain contact layer is formed over the upper portion. The source/drain contact layer is separated by the insulating layer from the bottom portion of the fin structure.

公开(公告)号：US10276719B1

公开(公告)日：2019-04-30

申请号：US15966761

申请日：2018-04-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Blandine Duriez ,  Gerben Doornbos ,  Mark Van Dal ,  Martin Christopher Holland

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L21/768

Abstract: In a method of manufacturing a semiconductor device, an opening is formed in an interlayer dielectric layer such that a source/drain region is exposed in the opening. A first semiconductor layer is formed to fully cover the exposed source/drain region within the opening. A heating process is performed to make an upper surface of the first semiconductor layer substantially flat. A conductive contact layer is formed over the first semiconductor layer.

公开(公告)号：US20140264277A1

公开(公告)日：2014-09-18

申请号：US13863489

申请日：2013-04-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Gerben Doornbos ,  Krishna Kumar Bhuwalka

IPC: H01L29/775 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/20 ,  H01L29/66356 ,  H01L29/66469 ,  H01L29/7391

Abstract: The present disclosure relates to an intra-band tunnel FET, which has a symmetric FET that is able to provide for a high drive current. In some embodiments, the disclosed intra-band tunnel FET has a source region having a first doping type and a drain region having the first doping type. The source region and the drain region are separated by a channel region. A gate region may generate an electric field that varies the position of a valence band and/or a conduction band in the channel region. By controlling the position of the valence band and/or the conduction band of the channel region, quantum mechanical tunneling of charge carries between the conduction band in the source region and in the drain region or between the valence band in the source region and in the drain region can be controlled.

Abstract translation: 本公开涉及带内隧道FET，其具有能够提供高驱动电流的对称FET。 在一些实施例中，所公开的带内隧道FET具有具有第一掺杂类型的源极区和具有第一掺杂类型的漏极区。 源极区域和漏极区域被沟道区域分开。 栅极区域可以产生改变通道区域中价带和/或导带的位置的电场。 通过控制通道区域的价带和/或导带的位置，电荷的量子力学隧道效应在源极区域和漏极区域中的导带之间或源极区域中的价带之间， 漏区可以控制。

公开(公告)号：US20240365569A1

公开(公告)日：2024-10-31

申请号：US18769091

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Marcus Johannes Henricus Van Dal ,  Timothy Vasen ,  Gerben Doornbos

IPC: H10K10/46 ,  H10K19/10 ,  H10K85/20

CPC classification number: H10K10/484 ,  H10K10/491 ,  H10K19/10 ,  H10K85/221

Abstract: The current disclosure describes techniques for forming semiconductor structures having multiple semiconductor strips configured as channel portions. In the semiconductor structures, diffusion break structures are formed after the gate structures are formed so that the structural integrity of the semiconductor strips adjacent to the diffusion break structures will not be compromised by a subsequent gate formation process. The diffusion break extends downward from an upper surface until all the semiconductor strips of the adjacent channel portions are truncated by the diffusion break.