公开(公告)号：US12089423B2

公开(公告)日：2024-09-10

申请号：US18311839

申请日：2023-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Marcus Johannes Henricus Van Dal ,  Timothy Vasen ,  Gerben Doornbos

IPC: H10K10/46 ,  H10K19/10 ,  H10K85/20

CPC classification number: H10K10/484 ,  H10K10/491 ,  H10K19/10 ,  H10K85/221

Abstract: The current disclosure describes techniques for forming semiconductor structures having multiple semiconductor strips configured as channel portions. In the semiconductor structures, diffusion break structures are formed after the gate structures are formed so that the structural integrity of the semiconductor strips adjacent to the diffusion break structures will not be compromised by a subsequent gate formation process. The diffusion break extends downward from an upper surface until all the semiconductor strips of the adjacent channel portions are truncated by the diffusion break.

公开(公告)号：US12051702B2

公开(公告)日：2024-07-30

申请号：US18167776

申请日：2023-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Matthias Passlack ,  Blandine Duriez ,  Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Mauricio Manfrini

IPC: H01L27/12 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1248 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02592 ,  H01L29/66757 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78675 ,  H01L29/78696 ,  H01L21/02645 ,  H01L21/02675 ,  H01L29/78618

Abstract: A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.

公开(公告)号：US20230197445A1

公开(公告)日：2023-06-22

申请号：US18167776

申请日：2023-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Matthias Passlack ,  Blandine Duriez ,  Georgios Vellianitis ,  Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Mauricio Manfrini

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L21/02488 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78675 ,  H01L21/02645 ,  H01L21/02675 ,  H01L29/66757 ,  H01L29/78648 ,  H01L29/78696 ,  H01L21/02532 ,  H01L21/02592

Abstract: A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.

公开(公告)号：US11557726B2

公开(公告)日：2023-01-17

申请号：US17068736

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Marcus Johannes Henricus Van Dal ,  Gerben Doornbos ,  Matthias Passlack

IPC: H01L21/00 ,  H01L51/00 ,  C23C16/455 ,  C23C16/56 ,  H01L23/544 ,  H01L51/05

Abstract: Provided herein are wafers that can be used to align carbon nanotubes, as well as methods of making and using the same. Such wafers include alignment areas that have four sides and a surface charge, where the alignment areas are surrounded by areas that have a surface charge of a different polarity. Methods of the disclosure may include depositing and selectively etching a number of hardmasks on a substrate. The described methods may also include depositing a carbon nanotube on such a wafer.

公开(公告)号：US11437594B2

公开(公告)日：2022-09-06

申请号：US16940321

申请日：2020-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Timothy Vasen ,  Mark Van Dal ,  Gerben Doornbos ,  Matthias Passlack

IPC: H01L51/05 ,  H01L27/28 ,  H01L51/00

Abstract: In a method of forming a gate-all-around field effect transistor (GAA FET), a bottom support layer is formed over a substrate and a first group of carbon nanotubes (CNTs) are disposed over the bottom support layer. A first support layer is formed over the first group of CNTs and the bottom support layer such that the first group of CNTs are embedded in the first support layer. A second group of carbon nanotubes (CNTs) are disposed over the first support layer. A second support layer is formed over the second group of CNTs and the first support layer such that the second group of CNTs are embedded in the second support layer. A fin structure is formed by patterning at least the first support layer and the second support layer.

公开(公告)号：US20220223744A1

公开(公告)日：2022-07-14

申请号：US17706199

申请日：2022-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Blandine Duriez ,  Marcus Johannes Henricus Van Dal ,  Martin Christopher Holland ,  Gerben Doornbos ,  Georgios Vellianitis

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L21/268 ,  H01L21/285 ,  H01L21/324 ,  H01L21/311

Abstract: A method of forming a semiconductor device includes forming source/drain contact openings extending through at least one dielectric layer to expose source/drain contact regions of source/drain structures. The method further includes depositing a light blocking layer along sidewalls and bottom surfaces of the source/drain contact openings and a topmost surface of the at least one dielectric layer. The method further includes performing a laser annealing process to activate dopants in the source/drain contact region. The method further includes forming source/drain contact structures within source/drain contact openings.

公开(公告)号：US11349022B2

公开(公告)日：2022-05-31

申请号：US16889600

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Gerben Doornbos ,  Matthias Passlack

IPC: H01L29/66 ,  H01L29/775 ,  H01L29/205 ,  H01L29/10 ,  H01L29/08

Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.

公开(公告)号：US11264506B2

公开(公告)日：2022-03-01

申请号：US16658768

申请日：2019-10-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Marcus Johannes Henricus Van Dal ,  Gerben Doornbos

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/24 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a power switch circuit and a logic circuit. The semiconductor device includes a first dielectric layer and a thin film transistor (TFT) formed on the first dielectric layer. The TFT includes a semiconductor nano-sheet, a gate dielectric layer wrapping around a channel region of the semiconductor nano-sheet, and a gate electrode layer formed on the gate dielectric layer. The semiconductor nano-sheet is made of an oxide semiconductor material.

公开(公告)号：US20210376107A1

公开(公告)日：2021-12-02

申请号：US16888349

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Marcus Johannes Henricus van Dal ,  Gerben Doornbos ,  Georgios Vellianitis

IPC: H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first gate electrode, a ferroelectric insulating layer over the first gate electrode, a semiconductor member over the ferroelectric insulating layer, a gate dielectric layer over the semiconductor member, and a second gate electrode over the gate dielectric layer.

公开(公告)号：US10971684B2

公开(公告)日：2021-04-06

申请号：US16412810

申请日：2019-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mauricio Manfrini ,  Chung-Te Lin ,  Gerben Doornbos ,  Marcus Johannes Henricus van Dal

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: Some embodiments relate to an integrated chip including a memory device. The memory device includes a bottom electrode disposed over a semiconductor substrate. An upper electrode is disposed over the bottom electrode. An intercalated metal/dielectric structure is sandwiched between the bottom electrode and the upper electrode. The intercalated metal/dielectric structure comprises a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.