公开(公告)号：US11508666B2

公开(公告)日：2022-11-22

申请号：US16914480

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sen-Kuei Hsu ,  Hsin-Yu Pan ,  Chien-Chang Lin

IPC: H01L29/00 ,  H01L23/538 ,  H03H7/01 ,  H01L23/66 ,  H01P3/08

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage.

公开(公告)号：US20220367301A1

公开(公告)日：2022-11-17

申请号：US17875656

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Teng-Yuan Lo ,  Lipu Kris Chuang ,  Hsin-Yu Pan

IPC: H01L23/24 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.

公开(公告)号：US11309302B2

公开(公告)日：2022-04-19

申请号：US16898409

申请日：2020-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Chen ,  Chih-Hua Chen ,  Hsin-Yu Pan ,  Hao-Yi Tsai ,  Lipu Kris Chuang ,  Tin-Hao Kuo

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/31 ,  H01L23/34 ,  H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538 ,  H01L25/10 ,  H01L21/683

Abstract: Manufacturing method of semiconductor package includes following steps. Bottom package is provided. The bottom package includes a die and a redistribution structure electrically connected to die. A first top package and a second top package are disposed on a surface of the redistribution structure further away from the die. An underfill is formed into the space between the first and second top packages and between the first and second top packages and the bottom package. The underfill covers at least a side surface of the first top package and a side surface of the second top package. A hole is opened in the underfill within an area overlapping with the die between the side surface of the first top package and the side surface of the second top package. A thermally conductive block is formed in the hole by filling the hole with a thermally conductive material.

公开(公告)号：US20210407914A1

公开(公告)日：2021-12-30

申请号：US16914480

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sen-Kuei Hsu ,  Hsin-Yu Pan ,  Chien-Chang Lin

IPC: H01L23/538 ,  H03H7/01 ,  H01L23/66 ,  H01P3/08

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage.

公开(公告)号：US20210202354A1

公开(公告)日：2021-07-01

申请号：US16897300

申请日：2020-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lipu Kris Chuang ,  Chung-Shi Liu ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Ming-Kai Liu ,  Ting-Chu Ko

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/31 ,  H01L23/367 ,  H01L21/56 ,  H01L21/48

Abstract: A memory device including a base chip and a memory cube mounted on and connected with the base chip is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes semiconductor chips laterally wrapped by an encapsulant and a redistribution structure. The semiconductor chips of the multiple stacked tiers are electrically connected with the base chip through the redistribution structures in the multiple stacked tiers. The memory cube includes a thermal path structure extending through the multiple stacked tiers and connected to the base chip. The thermal path structure has a thermal conductivity larger than that of the encapsulant. The thermal path structure is electrically isolated from the semiconductor chips in the multiple stacked tiers and the base chip.

公开(公告)号：US20210183760A1

公开(公告)日：2021-06-17

申请号：US17188787

申请日：2021-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Wen Shih ,  Chen-Hua Yu ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Hao-Yi Tsai ,  Sen-Kuei Hsu

IPC: H01L23/525 ,  H01L23/552 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56

Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.

公开(公告)号：US11018113B2

公开(公告)日：2021-05-25

申请号：US16655237

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lipu Kris Chuang ,  Chung-Hao Tsai ,  Hsin-Yu Pan ,  Yi-Che Chiang ,  Chien-Chang Lin

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/373 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56 ,  H01L23/367

Abstract: A memory module includes a first redistribution structure, a second redistribution structure, first semiconductor dies, second semiconductor dies, an encapsulant, through insulator vias and thermally conductive material. Second redistribution structure is stacked over first redistribution structure. First semiconductor dies are sandwiched between first redistribution structure and second redistribution structure and disposed side by side. Second semiconductor dies are disposed on the second redistribution structure. The encapsulant laterally wraps the second semiconductor dies. The through insulator vias are disposed among the first semiconductor dies, extending from the first redistribution structure to the second redistribution structure. The through insulator vias are electrically connected to the first redistribution structure and the second redistribution structure. The thermally conductive material is disposed on the second redistribution structure, among the second semiconductor dies and overlying the through insulator vias. The thermally conductive material has a thermal conductivity larger than that of the encapsulant.

公开(公告)号：US10748831B2

公开(公告)日：2020-08-18

申请号：US15992196

申请日：2018-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sen-Kuei Hsu ,  Ching-Feng Yang ,  Hsin-Yu Pan ,  Kai-Chiang Wu ,  Yi-Che Chiang

IPC: H01L23/36 ,  H01L23/52 ,  H01L23/538 ,  H01L23/367 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522

Abstract: Semiconductor packages and methods of forming the same are provided. One of the semiconductor package includes a first die, a dummy die, a first redistribution layer structure, an insulating layer and an insulating layer. The dummy die is disposed aside the first die. The first redistribution layer structure is electrically connected to the first die and having connectors thereover. The insulating layer is disposed over the first die and the dummy die and opposite to the first redistribution layer structure. The insulating layer penetrates through the insulating layer.

公开(公告)号：US20200091031A1

公开(公告)日：2020-03-19

申请号：US16693386

申请日：2019-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Chao-Wen Shih ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Sen-Kuei Hsu

IPC: H01L23/367 ,  H01L23/66 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L21/683 ,  H01Q1/02 ,  H01Q21/08

Abstract: A semiconductor package, a semiconductor device and a method for packaging the semiconductor device are provided. A semiconductor package includes a first conductive wire layer with a first mounting area and a second mounting area, an integrated circuit (IC), a radiation fin structure and an antenna. The first mounting area and the second mounting area do not overlap. The IC is disposed on a first surface of the first mounting area. The radiation fin structure is disposed on a second surface of the first mounting area. The antenna is disposed on the second mounting area.

公开(公告)号：US20190371694A1

公开(公告)日：2019-12-05

申请号：US15992196

申请日：2018-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sen-Kuei Hsu ,  Ching-Feng Yang ,  Hsin-Yu Pan ,  Kai-Chiang Wu ,  Yi-Che Chiang

IPC: H01L23/367 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/538

Abstract: Semiconductor packages and methods of forming the same are provided. One of the semiconductor package includes a first die, a dummy die, a first redistribution layer structure, an insulating layer and an insulating layer. The dummy die is disposed aside the first die. The first redistribution layer structure is electrically connected to the first die and having connectors thereover. The insulating layer is disposed over the first die and the dummy die and opposite to the first redistribution layer structure. The insulating layer penetrates through the insulating layer.