公开(公告)号：US11574857B2

公开(公告)日：2023-02-07

申请号：US16827595

申请日：2020-03-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Feng Yang ,  Hsin-Yu Pan ,  Kai-Chiang Wu ,  Chien-Chang Lin

IPC: H01L23/498 ,  H01L21/52 ,  H01L23/16 ,  H01L21/48 ,  H01L25/18

Abstract: A semiconductor package includes a circuit board structure, a redistribution layer structure, a package structure, and a ring structure. The redistribution layer structure has a first region and a second region surrounding the first region. The redistribution layer structure is disposed over and electrically connected to the circuit board structure. A metal density in the second region is greater than a metal density in the first region. The package structure is disposed over the first region of the redistribution layer structure. The package structure is electrically connected to the redistribution layer structure. The ring structure is disposed over the second region of the redistribution layer structure.

公开(公告)号：US20220320024A1

公开(公告)日：2022-10-06

申请号：US17844876

申请日：2022-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Hsiang Chuang ,  Shih-Wei Liang ,  Ching-Feng Yang ,  Kai-Chiang Wu ,  Hao-Yi Tsai ,  Chuei-Tang Wang ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L23/495 ,  H01L21/768 ,  H01L23/522 ,  H01L23/525 ,  H01L23/532 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00

Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.

公开(公告)号：US11018083B2

公开(公告)日：2021-05-25

申请号：US16513727

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tuan-Yu Hung ,  Ching-Feng Yang ,  Hung-Jui Kuo ,  Kai-Chiang Wu ,  Ming-Che Ho

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L23/66 ,  H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01Q1/22 ,  H01Q9/04 ,  H01Q9/28

Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a semiconductor die, a through via structure, a dipole structure and an encapsulant. The through via structure and the dipole structure are disposed aside the semiconductor die, and respectively includes an insulating core and a conductive layer. A front surface and a sidewall of the insulating core are covered by the conductive layer. The semiconductor die, the through via structure and the dipole structure are laterally encapsulated by the encapsulant. Surfaces of capping portions of the conductive layers covering the front surfaces of the insulating cores are substantially coplanar with a front surface of the encapsulant.

公开(公告)号：US20190123017A1

公开(公告)日：2019-04-25

申请号：US16223274

申请日：2018-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Lin Lu ,  Kai-Chiang Wu ,  Ming-Kai Liu ,  Yen-Ping Wang ,  Shih-Wei Liang ,  Ching-Feng Yang ,  Chia-Chun Miao ,  Hung-Jen Lin

IPC: H01L23/00

Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.

公开(公告)号：US20210296221A1

公开(公告)日：2021-09-23

申请号：US16827595

申请日：2020-03-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Feng Yang ,  Hsin-Yu Pan ,  Kai-Chiang Wu ,  Chien-Chang Lin

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/52 ,  H01L23/16

Abstract: A semiconductor package includes a circuit board structure, a redistribution layer structure, a package structure, and a ring structure. The redistribution layer structure has a first region and a second region surrounding the first region. The redistribution layer structure is disposed over and electrically connected to the circuit board structure. A metal density in the second region is greater than a metal density in the first region. The package structure is disposed over the first region of the redistribution layer structure. The package structure is electrically connected to the redistribution layer structure. The ring structure is disposed over the second region of the redistribution layer structure.

公开(公告)号：US09559071B2

公开(公告)日：2017-01-31

申请号：US13927972

申请日：2013-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Chun-Lin Lu ,  Kai-Chiang Wu ,  Ming-Kai Liu ,  Yen-Ping Wang ,  Shih-Wei Liang ,  Ching-Feng Yang ,  Chia-Chun Miao ,  Hung-Jen Lin

IPC: H01L29/24 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/81 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03472 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0554 ,  H01L2224/05559 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/11015 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/1319 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14179 ,  H01L2224/14505 ,  H01L2224/1601 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/17517 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81148 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/207 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.

Abstract translation: 提供了用于形成封装结构的机构的实施例。 封装结构包括半导体管芯和衬底。 封装结构包括柱状凸起和与半导体管芯和衬底结合的细长焊料凸块。 细长焊料凸块的高度基本上等于柱形凸块的高度。 细长的焊料凸块在通过细长焊料凸块的侧壁表面的上端的第一水平面处具有第一宽度，并且在通过侧壁表面的中点的第二水平面处具有第二宽度。 第二宽度与第一宽度的比率在约0.5至约1.1的范围内。

公开(公告)号：US20210391230A1

公开(公告)日：2021-12-16

申请号：US17462115

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Lin Lu ,  Kai-Chiang Wu ,  Yen-Ping Wang ,  Shih-Wei Liang ,  Ching-Feng Yang

IPC: H01L23/24 ,  H05K1/18 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L25/10

Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.

公开(公告)号：US20210020559A1

公开(公告)日：2021-01-21

申请号：US16513727

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tuan-Yu Hung ,  Ching-Feng Yang ,  Hung-Jui Kuo ,  Kai-Chiang Wu ,  Ming-Che Ho

IPC: H01L23/498 ,  H01L23/00 ,  H01Q1/22 ,  H01Q9/04 ,  H01Q9/28 ,  H01L21/768 ,  H01L21/56 ,  H01L23/66 ,  H01L23/31 ,  H01L23/48

Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a semiconductor die, a through via structure, a dipole structure and an encapsulant. The through via structure and the dipole structure are disposed aside the semiconductor die, and respectively includes an insulating core and a conductive layer. A front surface and a sidewall of the insulating core are covered by the conductive layer. The semiconductor die, the through via structure and the dipole structure are laterally encapsulated by the encapsulant. Surfaces of capping portions of the conductive layers covering the front surfaces of the insulating cores are substantially coplanar with a front surface of the encapsulant.

公开(公告)号：US20200373219A1

公开(公告)日：2020-11-26

申请号：US16993285

申请日：2020-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sen-Kuei Hsu ,  Ching-Feng Yang ,  Hsin-Yu Pan ,  Kai-Chiang Wu ,  Yi-Che Chiang

IPC: H01L23/367 ,  H01L21/768 ,  H01L23/00 ,  H01L23/538 ,  H01L23/522

Abstract: A semiconductor package includes a die, a dummy die, a plurality of conductive terminals, an insulating layer and a plurality of thermal through vias. The dummy die is disposed aside the die. The conductive terminals are disposed at a first side of the dummy die and the die and electrically connected to the dummy die and the die. The insulating layer is disposed at a second side opposite to the first side of the dummy die and the die. The thermal through vias penetrating through the insulating layer.

公开(公告)号：US20200303331A1

公开(公告)日：2020-09-24

申请号：US16893422

申请日：2020-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang-Yu Liang ,  Ching-Feng Yang ,  Kai-Chiang Wu

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/538 ,  H01L23/552 ,  H01L23/31 ,  H01L25/16 ,  H01L21/56 ,  H01L21/683 ,  H01L21/3205 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/288 ,  H01L21/321 ,  H01L21/48 ,  H01Q1/40

Abstract: A method including followings is provided. An encapsulated device including a semiconductor die and an insulating encapsulation laterally encapsulating the semiconductor die is provided. An insulating layer is formed over a surface of the encapsulated device. A groove pattern is formed on the insulating layer. A conductive paste is filled in the groove pattern and the conductive paste filled in the groove pattern is cured.