公开(公告)号：US20230275095A1

公开(公告)日：2023-08-31

申请号：US18312844

申请日：2023-05-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy LIAW

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L27/0924 ,  H01L29/785 ,  H01L29/41791

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a gate structure, a source structure, a drain structure, a source contact, and a drain contact. The semiconductor fin extends upwardly from the substrate. The gate structure extends across the semiconductor fin. The source structure is on the semiconductor fin. The drain structure is on the semiconductor fin, in which the source and drain structures are respectively on opposite sides of the gate structure in a plan view. The source contact lands on the source structure and forms a rectangular pattern in the plan view. The drain contact lands on the drain structure and forms a circular pattern in the plan view, in which the rectangular pattern of the source contact has a length greater than a longest dimension of the circular pattern of the drain contact.

公开(公告)号：US20230261053A1

公开(公告)日：2023-08-17

申请号：US18309181

申请日：2023-04-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy LIAW

IPC: H01L29/08 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/088 ,  H10B10/00

CPC classification number: H01L29/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/41791 ,  H01L27/0886 ,  H10B10/12

Abstract: An integrated circuit (IC) structure includes a substrate and a fin structure. The substrate includes a first cell region and a second cell region abutting the first cell region. The fin structure includes a first plan-view profile within the first cell region and a second plan-view profile within the second cell region. The first plan-view profile includes a first sidewall and a second sidewall opposing the first sidewall. The second plan-view profile includes a third sidewall and a fourth sidewall opposing the third sidewall. A width between the first sidewall and the second sidewall is greater than a width between the third sidewall and the fourth sidewall.

公开(公告)号：US20230260848A1

公开(公告)日：2023-08-17

申请号：US18306113

申请日：2023-04-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy LIAW

IPC: H01L21/8238 ,  H01L21/311 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L21/823821 ,  H01L21/31144 ,  H01L21/823814 ,  H01L29/785 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795 ,  H01L21/823878

Abstract: A method for manufacturing a semiconductor device includes forming first and second semiconductor fins extending upwardly from a substrate; forming a dielectric fin between the first and second semiconductor fins; forming a shallow trench isolation (STI) structure laterally surrounding lower portions of the first and second semiconductor fins and the dielectric fin; forming a gate strip extending across upper portions of the first semiconductor fin, the dielectric fin, and the second semiconductor fin; patterning the gate strip to form a first gate structure extending across the first semiconductor fin and a second gate structure extending across the second semiconductor fin while leaving the dielectric fin uncovered; and after patterning the gate strip, depositing a high-k dielectric material over the dielectric fin and in contact with a longitudinal end of the first gate structure and a longitudinal end of the second gate structure.

公开(公告)号：US20220172999A1

公开(公告)日：2022-06-02

申请号：US17671451

申请日：2022-02-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Dian-Sheg YU ,  Ren-Fen TSUI ,  Jhon-Jhy LIAW

IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device includes first and second semiconductor fins, first, second, third and fourth gate structures, and a dielectric structure. The first semiconductor fin and the second semiconductor fin are over a substrate. The first gate structure and the second gate structure respectively extend across the first semiconductor fin and the second semiconductor fin. The first gate structure has a longitudinal axis aligned with a longitudinal axis of the second gate structure. The dielectric structure interposes the first gate structure and the second gate structure. The third gate structure extends across the first and second semiconductor fins. The fourth gate structure extends across the first and second semiconductor fins. The third gate structure is between the fourth gate structure and the dielectric structure. The third gate structure has a maximal width greater than a maximal width of the four gate structure.

公开(公告)号：US20210343725A1

公开(公告)日：2021-11-04

申请号：US17373675

申请日：2021-07-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy LIAW

IPC: H01L27/11 ,  H01L29/423 ,  H01L27/02 ,  H01L27/092 ,  H01L29/161 ,  G11C11/419 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/3213

Abstract: An IC structure comprises a substrate, a first SRAM cell, and a second SRAM cell. The first SRAM cell is formed over the substrate and comprises a first N-type transistor. The second SRAM cell is formed over the substrate and comprises a second N-type transistor. A gate structure of first N-type transistor of the first SRAM cell has a different work function metal composition than a gate structure of the second N-type transistor of the second SRAM cell.

公开(公告)号：US20200266271A1

公开(公告)日：2020-08-20

申请号：US16868625

申请日：2020-05-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ta-Chun LIN ,  Kuo-Hua PAN ,  Jhon-Jhy LIAW ,  Chao-Ching CHENG ,  Hung-Li CHIANG ,  Shih-Syuan HUANG ,  Tzu-Chiang CHEN ,  I-Sheng CHEN ,  Sai-Hooi YEONG

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L21/8234

Abstract: Methods for forming semiconductor structures are provided. The method includes alternately stacking first semiconductor layers and second semiconductor layers over a substrate and patterning the first semiconductor layers and the second semiconductor layers to form a first fin structure. The method further includes forming a first trench in the first fin structure and forming a first source/drain structure in the first trench. The method further includes partially removing the first source/drain structure to form a second trench in the first source/drain structure and forming a first contact in the second trench.

公开(公告)号：US20200051618A1

公开(公告)日：2020-02-13

申请号：US16660242

申请日：2019-10-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy LIAW

IPC: G11C11/412 ,  H01L27/11

Abstract: SRAM arrays are provided. In each SRAM cell arranged in a column of cell array, a pull-down transistor and a pass-gate transistor are formed in P-type well region. A pull-up transistor is formed in N-type well region. At least one well strap cell includes an N-well strap structure formed on the N-type well region and a P-well strap structure formed on the P-type well region. A first distance between the active region of the P-well strap structure and the N-type well region is greater than a second distance between an active region of the pull-down transistor and the pass-gate transistor and the N-type well region.

公开(公告)号：US20190386012A1

公开(公告)日：2019-12-19

申请号：US16530404

申请日：2019-08-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hung HSIEH ,  Yu-Min LIAO ,  Jhon-Jhy LIAW

IPC: H01L27/11 ,  G11C11/412

Abstract: SRAM structures are provided. A SRAM structure includes multiple SRAM cells arranged in multiple rows and multiple columns. A first SRAM cell is adjacent to a second SRAM cell in the same row. A third SRAM cell is adjacent to the first SRAM cell in the same column. A fourth SRAM cell is adjacent to the second SRAM in the same column. A contact plug is positioned between the first, second, third and fourth SRAM cells. A VSS line is electrically coupled to the first, second, third and fourth SRAM cells through the contact plug. The contact plug is free of the barrier layer.

公开(公告)号：US20190363024A1

公开(公告)日：2019-11-28

申请号：US16532067

申请日：2019-08-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Dian-Sheg YU ,  Ren-Fen TSUI ,  Jhon-Jhy LIAW

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/78 ,  H01L27/092 ,  H01L27/11 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/28 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate having a semiconductor fin, an isolation feature over the substrate and not overlapping the semiconductor fin, a first gate structure over the substrate, and a second gate structure over the substrate. The isolation feature is closer to the first gate structure than the second gate structure. The first gate structure has a maximum width greater than a maximum width of the second gate structure.

公开(公告)号：US20190288080A1

公开(公告)日：2019-09-19

申请号：US16429217

申请日：2019-06-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy LIAW

IPC: H01L29/40 ,  H01L29/78 ,  H01L27/088 ,  H01L27/12 ,  H01L27/092 ,  H01L29/66 ,  H01L29/417 ,  H01L21/84 ,  H01L21/8238 ,  H01L23/485

Abstract: A semiconductor device includes a first semiconductor structure, a second semiconductor structure, a gate, and a gate contact. The first semiconductor structure and a second semiconductor structure are of different types. Each of the first semiconductor structure and the second semiconductor structure has a source, a drain and a channel region extends between the source and the drain. The gate extends across the channel regions of the first semiconductor structure and the second semiconductor structure. The gate contact directly is on the gate. The gate contact has a strip shape of which a ratio of a length to a width is at least 2 and includes a gate conductive plug and a gate contact dielectric. The gate conductive plug is directly in contact with the gate. The gate contact dielectric surrounds side surfaces of the gate conductive plug and having a frame shape.