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    Semiconductor package and manufacturing method thereof
    41.
    发明授权
    Semiconductor package and manufacturing method thereof 有权

    公开(公告)号：US11069662B2

    公开(公告)日：2021-07-20

    申请号：US16882517

    申请日：2020-05-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jie Chen ,  Hsien-Wei Chen

    IPC: H01L25/07 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

    Abstract: A semiconductor package includes a first chip package including a plurality of first semiconductor dies and a first insulating encapsulant, a second semiconductor die, a third semiconductor die, and a second insulating encapsulant. The plurality of first semiconductor dies are electrically connected to each other, and the first insulating encapsulant encapsulates the plurality of first semiconductor dies. The second semiconductor die and the third semiconductor die are electrically communicated to each other by connecting to the first chip package, wherein the first chip package is stacked on the second semiconductor die and the third semiconductor die. The second insulating encapsulant encapsulates the first chip package, the second semiconductor die, and the third semiconductor die.

    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    44.
    发明申请
    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20210091022A1

    公开(公告)日：2021-03-25

    申请号：US16919068

    申请日：2020-07-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming-Fa Chen ,  Hsien-Wei Chen ,  Jie Chen

    IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an integrated circuit (IC) component, an insulating layer laterally encapsulating sidewalls of the IC component, a redistribution structure disposed on the insulating layer and the IC component, and a warpage control portion coupling to a back side of the IC component opposite to the redistribution structure. The redistribution structure is electrically connected to the IC component. The warpage control portion includes a substrate, a patterned dielectric layer disposed between the substrate and the IC component, and a metal pattern embedded in the patterned dielectric layer and electrically isolated from the IC component.

    Semiconductor package and manufacturing method thereof
    47.
    发明授权
    Semiconductor package and manufacturing method thereof 有权

    公开(公告)号：US10665572B2

    公开(公告)日：2020-05-26

    申请号：US16103939

    申请日：2018-08-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jie Chen ,  Hsien-Wei Chen

    IPC: H01L25/07 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

    Abstract: A semiconductor package includes a first chip package including a plurality of first semiconductor dies and a first insulating encapsulant, a second semiconductor die, a third semiconductor die, and a second insulating encapsulant. The plurality of first semiconductor dies are electrically connected to each other, and the first insulating encapsulant encapsulates the plurality of first semiconductor dies. The second semiconductor die and the third semiconductor die are electrically communicated to each other by connecting to the first chip package, wherein the first chip package is stacked on the second semiconductor die and the third semiconductor die. The second insulating encapsulant encapsulates the first chip package, the second semiconductor die, and the third semiconductor die.

    Three-dimensional integrated circuit structures
    48.
    发明授权
    Three-dimensional integrated circuit structures 有权

    公开(公告)号：US10504852B1

    公开(公告)日：2019-12-10

    申请号：US16016658

    申请日：2018-06-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jie Chen ,  Hsien-Wei Chen ,  Ying-Ju Chen

    IPC: H01L23/544 ,  H01L23/522 ,  H01L25/065 ,  H01L23/528

    Abstract: Three-dimensional integrated circuit (3DIC) structures are disclosed. A 3DIC structure includes a first die and a second die bonded to the first die. The first die includes a first integrated circuit region and a first seal ring region around the first integrated circuit region, and has a first alignment mark within the first integrated circuit region. The second die includes a second integrated circuit region and a second seal ring region around the second integrated circuit region, and has a second alignment mark within the second seal ring region and corresponding to the first alignment mark.

    Method of forming a semiconductor device with bump stop structure
    49.
    发明授权
    Method of forming a semiconductor device with bump stop structure 有权

    公开(公告)号：US10269749B2

    公开(公告)日：2019-04-23

    申请号：US15194160

    申请日：2016-06-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jie Chen ,  Hsien-Wei Chen

    IPC: H01L21/768 ,  H01L23/485 ,  H01L23/00 ,  H01L23/31 ,  H01L23/525 ,  H01L23/532 ,  H01L23/29

    Abstract: A method for manufacturing semiconductor devices is provided. A protection layer is conformally deposited over a passivation layer such that the protection layer has a protrusion pattern that protrudes from a top surface of the protection layer. Further, a post-passivation interconnect structure (PPI) is conformally formed on the protection layer such that the PPI structure includes a landing pad region, a protrusion pattern conformal to the protrusion pattern of the protection layer, and a connection line electrically connected to the conductive pad. A solder bump is then placed on the landing pad region in contact with the protrusion pattern of PPI structure. A semiconductor device with bump stop structure is also provided. The protrusion pattern of the PPI structure serves as a bump stop that constrains a ball shift in the placement of the solder bump over the landing pad.

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