公开(公告)号：US12154876B2

公开(公告)日：2024-11-26

申请号：US17813865

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065

Abstract: A semiconductor device includes a first interconnect structure over first substrate, a first bonding layer over the first interconnect structure, multiple first bonding pads disposed in a first region of the first bonding layer, the first bonding pads having a first pitch, and multiple second bonding pads disposed in a second region of the first bonding layer, the second region extending between a first edge of the first bonding layer and the first region, the second bonding pads having the first pitch, the multiple second bonding pads including multiple pairs of adjacent second bonding pads, wherein the second bonding pads of each respective pair are connected by a first metal line.

公开(公告)号：US20240379598A1

公开(公告)日：2024-11-14

申请号：US18784164

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Hsien-Wei Chen ,  Jie Chen

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/538

Abstract: A package includes a first die that includes a first metallization layer, one or more first bond pad vias on the first metallization layer, wherein a first barrier layer extends across the first metallization layer between each first bond pad via and the first metallization layer, and one or more first bond pads on the one or more first bond pad vias, wherein a second barrier layer extends across each first bond pad via between a first bond pad and the first bond pad via, and a second die including one or more second bond pads, wherein a second bond pad is bonded to a first bond pad of the first die.

公开(公告)号：US11996401B2

公开(公告)日：2024-05-28

申请号：US18302063

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen

IPC: H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L21/304

CPC classification number: H01L25/50 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3107 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/03 ,  H01L24/09 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/10 ,  H01L25/105 ,  H01L25/18 ,  H01L21/304 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/03003 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/0905 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13008 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13311 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2518 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/81005 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/92 ,  H01L2224/96 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/45144 ,  H01L2924/00 ,  H01L2224/96 ,  H01L2224/81 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/81447 ,  H01L2924/00014 ,  H01L2224/81411 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05611 ,  H01L2924/00014 ,  H01L2224/13166 ,  H01L2924/01029 ,  H01L2224/13181 ,  H01L2924/01029 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2224/13144 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/0105 ,  H01L2224/13139 ,  H01L2924/00014 ,  H01L2224/13164 ,  H01L2924/00014 ,  H01L2224/13109 ,  H01L2924/00014 ,  H01L2224/11462 ,  H01L2924/00014 ,  H01L2224/11452 ,  H01L2924/00014 ,  H01L2224/1145 ,  H01L2924/00014 ,  H01L2224/1132 ,  H01L2924/00014 ,  H01L2224/13294 ,  H01L2924/00014 ,  H01L2224/133 ,  H01L2924/014 ,  H01L2224/13311 ,  H01L2924/01047 ,  H01L2224/92 ,  H01L2221/68304 ,  H01L2224/03003 ,  H01L21/568 ,  H01L21/304 ,  H01L24/81 ,  H01L2221/68381 ,  H01L24/81 ,  H01L2224/92 ,  H01L2221/68304 ,  H01L2224/03 ,  H01L21/568 ,  H01L21/304 ,  H01L24/81 ,  H01L2221/68381 ,  H01L24/81 ,  H01L2224/05147 ,  H01L2924/00014 ,  H01L2224/05155 ,  H01L2924/00014 ,  H01L2224/05144 ,  H01L2924/00014 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05171 ,  H01L2924/01029 ,  H01L2224/05166 ,  H01L2924/01074 ,  H01L2224/05082 ,  H01L2224/05655 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05083 ,  H01L2224/05644 ,  H01L2224/05147 ,  H01L2224/05171 ,  H01L2924/01029 ,  H01L2224/05171 ,  H01L2224/05082 ,  H01L2224/05647 ,  H01L2224/05166 ,  H01L2924/01074 ,  H01L2224/05166 ,  H01L2224/05082 ,  H01L2224/05644 ,  H01L2224/05155 ,  H01L2224/05147 ,  H01L2224/45144 ,  H01L2924/00011 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45147 ,  H01L2924/00014 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.

公开(公告)号：US20240088122A1

公开(公告)日：2024-03-14

申请号：US18517330

申请日：2023-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen ,  Ming-Fa Chen ,  Chen-Hua Yu

IPC: H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/56 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A method of forming a package includes bonding a device die to an interposer wafer, with the interposer wafer including metal lines and vias, forming a dielectric region to encircle the device die, and forming a through-via to penetrate through the dielectric region. The through-via is electrically connected to the device die through the metal lines and the vias in the interposer wafer. The method further includes forming a polymer layer over the dielectric region, and forming an electrical connector. The electrical connector is electrically coupled to the through-via through a conductive feature in the polymer layer. The interposer wafer is sawed to separate the package from other packages.

公开(公告)号：US11855063B2

公开(公告)日：2023-12-26

申请号：US17181720

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen ,  Ming-Fa Chen ,  Chen-Hua Yu

IPC: H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/56 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A method of forming a package includes bonding a device die to an interposer wafer, with the interposer wafer including metal lines and vias, forming a dielectric region to encircle the device die, and forming a through-via to penetrate through the dielectric region. The through-via is electrically connected to the device die through the metal lines and the vias in the interposer wafer. The method further includes forming a polymer layer over the dielectric region, and forming an electrical connector. The electrical connector is electrically coupled to the through-via through a conductive feature in the polymer layer. The interposer wafer is sawed to separate the package from other packages.

公开(公告)号：US20230395517A1

公开(公告)日：2023-12-07

申请号：US17805036

申请日：2022-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Shin-Puu Jeng

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065 ,  H01L21/768

CPC classification number: H01L23/5386 ,  H01L24/32 ,  H01L24/29 ,  H01L25/105 ,  H01L25/0652 ,  H01L24/83 ,  H01L21/76898 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/32146 ,  H01L2224/83896 ,  H01L2224/2919 ,  H01L2224/29187 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1432 ,  H01L2924/37001

Abstract: A method includes joining a first wafer to a second wafer, forming a first through-via penetrating through the first wafer and further extending into the second wafer, and forming a redistribution line on the first wafer. The redistribution line and the first through-via electrically connect a first conductive feature in the first wafer to a second conductive feature in the second wafer. An electrical connector is formed over the first wafer.

公开(公告)号：US20230369262A1

公开(公告)日：2023-11-16

申请号：US18357818

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Hsien-Wei Chen ,  Jie Chen

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L24/05 ,  H01L21/76879 ,  H01L21/76843 ,  H01L23/5384

Abstract: A package includes a first die that includes a first metallization layer, one or more first bond pad vias on the first metallization layer, wherein a first barrier layer extends across the first metallization layer between each first bond pad via and the first metallization layer, and one or more first bond pads on the one or more first bond pad vias, wherein a second barrier layer extends across each first bond pad via between a first bond pad and the first bond pad via, and a second die including one or more second bond pads, wherein a second bond pad is bonded to a first bond pad of the first die.

公开(公告)号：US20230361027A1

公开(公告)日：2023-11-09

申请号：US17819381

申请日：2022-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yi Lin ,  Jie Chen ,  Sheng-Han Tsai ,  Yuan Sheng Chiu ,  Chou-Jui Hsu ,  Yu Kuei Yeh ,  Tsung-Shu Lin

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/00

CPC classification number: H01L23/528 ,  H01L23/53209 ,  H01L24/27 ,  H01L24/33 ,  H01L2224/33104

Abstract: A semiconductor device and method of manufacture are presented in which a first pad and a second pad are formed adjacent to each other. A first set of dummy pads is manufactured between the first pad and the second pad and bonding pads are formed in electrical connection to the first pad and the second pad.

公开(公告)号：US11735544B2

公开(公告)日：2023-08-22

申请号：US17315487

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Hsien-Wei Chen ,  Sung-Feng Yeh ,  Jie Chen

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05124 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die and a plurality of bumps. The first semiconductor die has a front side and a backside opposite to each other. The second semiconductor die is disposed at the backside of the first semiconductor die and electrically connected to first semiconductor die. The plurality of bumps is disposed at the front side of the first semiconductor die and physically connects first die pads of the first semiconductor die. A total width of the first semiconductor die may be less than a total width of the second semiconductor die.

公开(公告)号：US20230253354A1

公开(公告)日：2023-08-10

申请号：US18303302

申请日：2023-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L21/18

CPC classification number: H01L24/09 ,  H01L23/481 ,  H01L23/53238 ,  H01L24/03 ,  H01L21/76807 ,  H01L21/76871 ,  H01L21/187 ,  H01L2924/01013 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L33/0093

Abstract: A device includes an interconnect structure over a substrate, multiple first conductive pads over and connected to the interconnect structure, a planarization stop layer extending over the sidewalls and top surfaces of the first conductive pads of the multiple first conductive pads, a surface dielectric layer extending over the planarization stop layer, and multiple first bonding pads within the surface dielectric layer and connected to the multiple first conductive pads