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公开(公告)号：US20250118575A1
公开(公告)日：2025-04-10
申请号：US18984028
申请日：2024-12-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsien-Wei Chen , Ming-Fa Chen , Ying-Ju Chen
Abstract: A method of forming an integrated circuit package includes attaching a first die to an interposer. The interposer includes a first die connector and a second die connector on the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector. The first die is coupled to the first die connector and to the first dielectric layer and the second die connector is exposed by the first die. The method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connector and attaching a second die to the interposer, the second die being coupled to the second die connector.
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公开(公告)号：US20250069954A1
公开(公告)日：2025-02-27
申请号：US18948999
申请日：2024-11-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ying-Ju Chen , Hsien-Wei Chen
Abstract: A semiconductor device includes a plurality of connectors and at least one insulating layer disposed over a semiconductor substrate. A molding layer extends around the plurality of connectors. A sidewall of the molding layer that is closest to a scribe line is offset from the scribe line.
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公开(公告)号：US12176248B2
公开(公告)日：2024-12-24
申请号：US17391592
申请日：2021-08-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ying-Ju Chen , Hsien-Wei Chen
Abstract: A semiconductor device includes a plurality of connectors and at least one insulating layer disposed over a semiconductor substrate. A molding layer extends around the plurality of connectors. A sidewall of the molding layer that is closest to a scribe line is offset from the scribe line.
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公开(公告)号：US11862590B2
公开(公告)日：2024-01-02
申请号：US17361924
申请日：2021-06-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsien-Wei Chen , Ming-Fa Chen , Ying-Ju Chen
IPC: H01L25/065 , H01L23/00 , H01L25/18 , H01L21/56 , H01L25/00
CPC classification number: H01L24/08 , H01L21/565 , H01L24/80 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2225/06541 , H01L2225/06586 , H01L2225/06589 , H01L2924/1431 , H01L2924/1434
Abstract: A semiconductor package includes a redistribution structure, a first device and a second device attached to the redistribution structure, the first device including: a first die, a support substrate bonded to a first surface of the first die, and a second die bonded to a second surface of the first die opposite the first surface, where a total height of the first die and the second die is less than a first height of the second device, and where a top surface of the substrate is at least as high as a top surface of the second device, and an encapsulant over the redistribution structure and surrounding the first device and the second device.
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公开(公告)号：US20230369238A1
公开(公告)日：2023-11-16
申请号：US18358530
申请日：2023-07-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsien-Wei Chen , Ying-Ju Chen , Ming-Fa Chen
IPC: H01L23/544 , H01L21/74 , H01L21/78 , H01L23/31 , H01L23/525 , H01L23/58 , H01L23/00
CPC classification number: H01L23/544 , H01L21/74 , H01L21/78 , H01L23/3171 , H01L23/525 , H01L23/585 , H01L23/562
Abstract: A method of forming a semiconductor device includes: forming first electrical components in a substrate in a first device region of the semiconductor device; forming a first interconnect structure over and electrically coupled to the first electrical components; forming a first passivation layer over the first interconnect structure, the first passivation layer extending from the first device region to a scribe line region adjacent to the first device region; after forming the first passivation layer, removing the first passivation layer from the scribe line region while keeping a remaining portion of the first passivation layer in the first device region; and dicing along the scribe line region after removing the first passivation layer.
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Patent Agency Ranking
公开(公告)号：US20230317470A1
公开(公告)日：2023-10-05
申请号：US18329302
申请日：2023-06-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsien-Wei Chen , Ming-Fa Chen , Ying-Ju Chen
IPC: H01L21/56 , H01L21/78 , H01L23/31 , H01L23/538
CPC classification number: H01L21/563 , H01L21/78 , H01L23/31 , H01L23/5384 , H01L23/5386
Abstract: A method of forming an integrated circuit package includes attaching a first die to an interposer. The interposer includes a first die connector and a second die connector on the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector. The first die is coupled to the first die connector and to the first dielectric layer and the second die connector is exposed by the first die. The method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connector and attaching a second die to the interposer, the second die being coupled to the second die connector.
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公开(公告)号：US11735487B2
公开(公告)日：2023-08-22
申请号：US16919073
申请日：2020-07-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsien-Wei Chen , Ming-Fa Chen , Ying-Ju Chen
CPC classification number: H01L22/32 , H01L21/78 , H01L23/10 , H01L24/03 , H01L24/05 , H01L24/19 , H01L24/20
Abstract: A method includes the following steps. A semiconductor wafer including integrated circuit components, seal rings respectively encircling the integrated circuit components and testing structures disposed between the seal rings is provided. A first wafer saw process is performed at least along a first path to singulate the semiconductor wafer into a plurality of first singulated integrated circuit components each including a testing structure among the testing structures. When performing the first wafer saw process, testing pads of the testing structures are located beside the first path, such that a testing pad of a corresponding one of the testing structures in the first singulated integrated circuit component is laterally spaced apart from a sidewall of the first singulated integrated circuit component by a distance.
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公开(公告)号：US11705343B2
公开(公告)日：2023-07-18
申请号：US17328001
申请日：2021-05-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsien-Wei Chen , Ming-Fa Chen , Ying-Ju Chen
IPC: H01L21/56 , H01L21/78 , H01L23/31 , H01L23/538
CPC classification number: H01L21/563 , H01L21/78 , H01L23/31 , H01L23/5384 , H01L23/5386
Abstract: A method of forming an integrated circuit package includes attaching a first die to an interposer. The interposer includes a first die connector and a second die connector on the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector. The first die is coupled to the first die connector and to the first dielectric layer and the second die connector is exposed by the first die. The method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connector and attaching a second die to the interposer, the second die being coupled to the second die connector.
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公开(公告)号：US11699663B2
公开(公告)日：2023-07-11
申请号：US17006365
申请日：2020-08-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsien-Wei Chen , Ying-Ju Chen , Ming-Fa Chen
IPC: H01L21/00 , H01L23/544 , H01L21/74 , H01L21/78 , H01L23/31 , H01L23/525 , H01L23/58
CPC classification number: H01L23/544 , H01L21/74 , H01L21/78 , H01L23/3171 , H01L23/525 , H01L23/585
Abstract: A method of forming a semiconductor device includes: forming first electrical components in a substrate in a first device region of the semiconductor device; forming a first interconnect structure over and electrically coupled to the first electrical components; forming a first passivation layer over the first interconnect structure, the first passivation layer extending from the first device region to a scribe line region adjacent to the first device region; after forming the first passivation layer, removing the first passivation layer from the scribe line region while keeping a remaining portion of the first passivation layer in the first device region; and dicing along the scribe line region after removing the first passivation layer.
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公开(公告)号：US20220359470A1
公开(公告)日：2022-11-10
申请号：US17815390
申请日：2022-07-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chen-Hua Yu , An-Jhih Su , Wei-Yu Chen , Ying-Ju Chen , Tsung-Shu Lin , Chin-Chuan Chang , Hsien-Wei Chen , Wei-Cheng Wu , Li-Hsien Huang , Chi-Hsi Wu , Der-Chyang Yeh
IPC: H01L25/065 , H01L21/48 , H01L21/56 , H01L21/78 , H01L23/31 , H01L23/498 , H01L25/00
Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.
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