公开(公告)号：US20180351558A1

公开(公告)日：2018-12-06

申请号：US15965110

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng Wei KUO ,  Chewn-pu Jou ,  Huan-Neng Chen ,  Lan-Chou Cho ,  Robert Bogdan Staszewski ,  Seyednaser Pourmousavian

IPC: H03L1/00 ,  H03L7/093 ,  H03L7/099 ,  G04F10/00

CPC classification number: H03L1/00 ,  G04F10/005 ,  H03L7/093 ,  H03L7/0991

Abstract: An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations. The digital circuitry regulates the digital input supply voltage to stabilize the resolution of the TDC across the PVT variations. This stabilization of the resolution of the TDC can cause the ADPLL to maintain a fixed in-band phase noise across the PVT variations.

公开(公告)号：US09811056B2

公开(公告)日：2017-11-07

申请号：US15422523

申请日：2017-02-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Lan-Chou Cho ,  Chewn-Pu Jou ,  Feng-Wei Kuo ,  Huan-Neng Chen

IPC: H03M1/50 ,  G04F10/00 ,  H03K5/1534 ,  H03K5/131 ,  H03K5/00

CPC classification number: G04F10/005 ,  H03K5/131 ,  H03K5/135 ,  H03K5/1534 ,  H03K5/24 ,  H03K2005/00058 ,  H03K2005/00071

Abstract: A circuit includes a time delta detector configured to receive an input clock signal and a reference clock signal and generate a delta pulse signal and a reference pulse signal. A comparison circuit is configured to receive the delta pulse signal and the reference pulse signal. The comparison circuit generates an output indicative of a bit of a time difference between the input clock signal and the reference clock signal. A control circuit is configured to receive the output from the comparison circuit. The control circuit maintains a count of the time difference between the input clock signal and the reference clock signal.

公开(公告)号：US09571082B2

公开(公告)日：2017-02-14

申请号：US14689096

申请日：2015-04-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Lan-Chou Cho ,  Chewn-Pu Jou ,  Feng Wei Kuo ,  Huan-Neng Chen

IPC: H03K5/153 ,  H03K5/1534 ,  H03K5/135 ,  H03K5/13 ,  H03K5/24 ,  H03K5/00

CPC classification number: G04F10/005 ,  H03K5/131 ,  H03K5/135 ,  H03K5/1534 ,  H03K5/24 ,  H03K2005/00058 ,  H03K2005/00071

Abstract: A circuit includes a time delta detector configured to receive an input clock signal and a reference clock signal and generate a delta pulse signal and a reference pulse signal. A comparison circuit is configured to receive the delta pulse signal and the reference pulse signal. The comparison circuit generates an output indicative of a bit of a time difference between the input clock signal and the reference clock signal. A control circuit is configured to receive the output from the comparison circuit. The control circuit maintains a count of the time difference between the input clock signal and the reference clock signal.

Abstract translation: 一种电路包括时间差检测器，其被配置为接收输入时钟信号和参考时钟信号，并产生增量脉冲信号和参考脉冲信号。 比较电路被配置为接收增量脉冲信号和参考脉冲信号。 比较电路产生表示输入时钟信号和参考时钟信号之间的时间差的位的输出。 控制电路被配置为接收来自比较电路的输出。 控制电路维持输入时钟信号和参考时钟信号之间的时间差的计数。