公开(公告)号：US11621350B2

公开(公告)日：2023-04-04

申请号：US17403402

申请日：2021-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Youbo Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L29/40

Abstract: A semiconductor structure includes a gate stack on a semiconductor substrate and an etch stop layer disposed on the gate stack and the semiconductor substrate. The etch stop layer includes a first portion disposed on sidewalls of the gate stack and a second portion disposed on a top surface of the semiconductor substrate within a source/drain region. The semiconductor structure further includes a dielectric stress layer disposed on the second portion of the etch stop layer and being free from the first portion of the etch stop layer other than at a corner area formed by the first portion intersecting the second portion. The dielectric stress layer is different from the etch stop layer in composition and is configured to apply a compressive stress to a channel region underlying the gate stack.

公开(公告)号：US11302784B2

公开(公告)日：2022-04-12

申请号：US16746618

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Chang-Miao Liu ,  Ying-Keung Leung ,  Huiling Shang ,  Youbo Lin

IPC: H01L29/40 ,  H01L21/768 ,  H01L21/283 ,  H01L29/45 ,  H01L21/285 ,  H01L29/66

Abstract: A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide.

公开(公告)号：US20210104631A1

公开(公告)日：2021-04-08

申请号：US17122209

申请日：2020-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Chang-Miao Liu ,  Huiling Shang

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8238

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device of the present disclosure includes a first fin including a first source/drain region, a second fin including a second source/drain region, a first isolation layer disposed between the first source/drain region and the second source/drain region, and a second isolation layer disposed over the first isolation layer. A first portion of the first isolation layer is disposed on sidewalls of the first source/drain region and a second portion of the first isolation layer is disposed on sidewalls of the second source/drain region. A portion of the second isolation layer is disposed between the first portion and second portion of the first isolation layer.

公开(公告)号：US20210098309A1

公开(公告)日：2021-04-01

申请号：US16931703

申请日：2020-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Lun Min ,  Xusheng Wu ,  Chang-Miao Liu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/764

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; and a separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure.

公开(公告)号：US20210043502A1

公开(公告)日：2021-02-11

申请号：US17078677

申请日：2020-10-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu

IPC: H01L21/768 ,  H01L21/308 ,  H01L29/417 ,  H01L21/265 ,  H01L29/66 ,  H01L21/8234

Abstract: Source/drain contact spacers for improving integrated circuit device performance and methods of forming such are disclosed herein. An exemplary method includes etching an interlayer dielectric (ILD) layer to form a source/drain contact opening that exposes a contact etch stop layer (CESL) disposed over a source/drain feature, depositing a source/drain contact spacer layer that partially fills the source/drain contact opening and covers the ILD layer and the exposed CESL, and etching the source/drain contact spacer layer and the CESL to extend the source/drain contact opening to expose the source/drain feature. The etching forms source/drain contact spacers. The method further includes forming a source/drain contact to the exposed source/drain feature in the extended source/drain contact opening. The source/drain contact is formed over the source/drain contact spacers and fills the extended source/drain contact opening. A silicide feature can be formed over the exposed source/drain feature before forming the source/drain contact.

公开(公告)号：US20200006558A1

公开(公告)日：2020-01-02

申请号：US16192856

申请日：2018-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Chang-Miao Liu ,  Huiling Shang

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/225

Abstract: Examples of an integrated circuit with a strain-generating liner and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, and a gate disposed on the fin. The gate has a bottom portion disposed towards the fin and a top portion disposed on the bottom portion. A liner is disposed on a side surface of the bottom portion of the gate such that the top portion of the gate is free of the liner. In some such examples, the liner is configured to produce a channel strain.