公开(公告)号：US11948998B2

公开(公告)日：2024-04-02

申请号：US17815913

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Chang-Miao Liu ,  Huiling Shang

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/225 ,  H01L21/265 ,  H01L29/06

CPC classification number: H01L29/66742 ,  H01L21/7624 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66787 ,  H01L29/78603 ,  H01L29/78696 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/2253 ,  H01L21/26533 ,  H01L29/0673

Abstract: A method includes forming a semiconductor substrate having an oxide layer embedded therein, forming a multi-layer (ML) stack including alternating channel layers and non-channel layers over the semiconductor substrate, forming a dummy gate stack over the ML, forming an S/D recess in the ML to expose the oxide layer, forming an epitaxial S/D feature in the S/D recess, removing the non-channel layers from the ML to form openings between the channel layers, where the openings are formed adjacent to the epitaxial S/D feature, and forming a high-k metal gate stack (HKMG) in the openings between the channel layers and in place of the dummy gate stack.

公开(公告)号：US11855155B2

公开(公告)日：2023-12-26

申请号：US17658779

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Chang-Miao Liu ,  Ying-Keung Leung ,  Huiling Shang ,  Youbo Lin

IPC: H01L29/40 ,  H01L21/768 ,  H01L21/283 ,  H01L29/45 ,  H01L21/285 ,  H01L29/66

CPC classification number: H01L29/401 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L29/456 ,  H01L29/665

Abstract: A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide.

公开(公告)号：US20220310452A1

公开(公告)日：2022-09-29

申请号：US17213420

申请日：2021-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Ying-Keung Leung ,  Huiling Shang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor stack over a substrate, wherein the first semiconductor stack includes first semiconductor layers separated from each other and stacked up along a direction substantially perpendicular to a top surface of the substrate; second semiconductor stack over the substrate, wherein the second semiconductor stack includes second semiconductor layers separated from each other and stacked up along the direction substantially perpendicular to the top surface of the substrate; inner spacers between edge portions of the first semiconductor layers and between edge portions of the second semiconductor layers; and a bulk source/drain (S/D) feature between the first semiconductor stack and the second semiconductor stack, wherein the bulk S/D feature is separated from the substrate by a first air gap, and the bulk S/D feature is separated from the inner spacers by second air gaps.

公开(公告)号：US12148669B2

公开(公告)日：2024-11-19

申请号：US18524527

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Ying-Keung Leung ,  Huiling Shang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor stack over a substrate, wherein the first semiconductor stack includes first semiconductor layers separated from each other and stacked up along a direction substantially perpendicular to a top surface of the substrate; second semiconductor stack over the substrate, wherein the second semiconductor stack includes second semiconductor layers separated from each other and stacked up along the direction substantially perpendicular to the top surface of the substrate; inner spacers between edge portions of the first semiconductor layers and between edge portions of the second semiconductor layers; and a bulk source/drain (S/D) feature between the first semiconductor stack and the second semiconductor stack, wherein the bulk S/D feature is separated from the substrate by a first air gap, and the bulk S/D feature is separated from the inner spacers by second air gaps.

公开(公告)号：US20240105517A1

公开(公告)日：2024-03-28

申请号：US18524527

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Ying-Keung Leung ,  Huiling Shang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/823418 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/088 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/78696

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor stack over a substrate, wherein the first semiconductor stack includes first semiconductor layers separated from each other and stacked up along a direction substantially perpendicular to a top surface of the substrate; second semiconductor stack over the substrate, wherein the second semiconductor stack includes second semiconductor layers separated from each other and stacked up along the direction substantially perpendicular to the top surface of the substrate; inner spacers between edge portions of the first semiconductor layers and between edge portions of the second semiconductor layers; and a bulk source/drain (S/D) feature between the first semiconductor stack and the second semiconductor stack, wherein the bulk S/D feature is separated from the substrate by a first air gap, and the bulk S/D feature is separated from the inner spacers by second air gaps.

公开(公告)号：US11302784B2

公开(公告)日：2022-04-12

申请号：US16746618

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Chang-Miao Liu ,  Ying-Keung Leung ,  Huiling Shang ,  Youbo Lin

IPC: H01L29/40 ,  H01L21/768 ,  H01L21/283 ,  H01L29/45 ,  H01L21/285 ,  H01L29/66

Abstract: A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide.

公开(公告)号：US20210104631A1

公开(公告)日：2021-04-08

申请号：US17122209

申请日：2020-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Chang-Miao Liu ,  Huiling Shang

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8238

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device of the present disclosure includes a first fin including a first source/drain region, a second fin including a second source/drain region, a first isolation layer disposed between the first source/drain region and the second source/drain region, and a second isolation layer disposed over the first isolation layer. A first portion of the first isolation layer is disposed on sidewalls of the first source/drain region and a second portion of the first isolation layer is disposed on sidewalls of the second source/drain region. A portion of the second isolation layer is disposed between the first portion and second portion of the first isolation layer.

公开(公告)号：US20200006558A1

公开(公告)日：2020-01-02

申请号：US16192856

申请日：2018-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Chang-Miao Liu ,  Huiling Shang

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/225

Abstract: Examples of an integrated circuit with a strain-generating liner and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, and a gate disposed on the fin. The gate has a bottom portion disposed towards the fin and a top portion disposed on the bottom portion. A liner is disposed on a side surface of the bottom portion of the gate such that the top portion of the gate is free of the liner. In some such examples, the liner is configured to produce a channel strain.

公开(公告)号：US20240379442A1

公开(公告)日：2024-11-14

申请号：US18784531

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Ying-Keung Leung ,  Huiling Shang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor stack over a substrate, wherein the first semiconductor stack includes first semiconductor layers separated from each other and stacked up along a direction substantially perpendicular to a top surface of the substrate; second semiconductor stack over the substrate, wherein the second semiconductor stack includes second semiconductor layers separated from each other and stacked up along the direction substantially perpendicular to the top surface of the substrate; inner spacers between edge portions of the first semiconductor layers and between edge portions of the second semiconductor layers; and a bulk source/drain (S/D) feature between the first semiconductor stack and the second semiconductor stack, wherein the bulk S/D feature is separated from the substrate by a first air gap, and the bulk S/D feature is separated from the inner spacers by second air gaps.

公开(公告)号：US11837662B2

公开(公告)日：2023-12-05

申请号：US17122209

申请日：2020-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Chang-Miao Liu ,  Huiling Shang

IPC: H01L21/70 ,  H01L29/78 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8238

CPC classification number: H01L29/7846 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device of the present disclosure includes a first fin including a first source/drain region, a second fin including a second source/drain region, a first isolation layer disposed between the first source/drain region and the second source/drain region, and a second isolation layer disposed over the first isolation layer. A first portion of the first isolation layer is disposed on sidewalls of the first source/drain region and a second portion of the first isolation layer is disposed on sidewalls of the second source/drain region. A portion of the second isolation layer is disposed between the first portion and second portion of the first isolation layer.