公开(公告)号：US06829152B2

公开(公告)日：2004-12-07

申请号：US10310967

申请日：2002-12-06

申请人： Shoji Miura ,  Tomoatsu Makino ,  Fuminari Suzuki

发明人： Shoji Miura ,  Tomoatsu Makino ,  Fuminari Suzuki

IPC分类号： H02M114

CPC分类号： H01L29/7813 ,  H01L29/0638 ,  H01L29/7803 ,  H01L29/7805 ,  H01L29/7811 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/49175 ,  H01L2924/181 ,  H01L2924/19105 ,  H02M1/08 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A load drive circuit, disposed to drive an inductive load, includes a reflux closed circuit connected to the load. A flywheel diode is placed in the reflux closed circuit. A MOS transistor, disposed to turn on/off current to drive the load, is connected in parallel to the flywheel diode. A capacitor is disposed to connect its both ends to a gate and a drain of the MOS transistor, while a resistor is disposed to connect its both ends to the gate and a source of the MOS transistor. During a recovery operation of the flywheel diode, with the help of the capacitor and resistor, a gate-to-source voltage of the MOS transistor is pulled up to a value over a threshold for a predetermined period of time. Pulling up the gate-to-source voltage results in a softened recovery characteristic of the flywheel diode, suppressing recovery surges.

摘要翻译： 设置用于驱动感性负载的负载驱动电路包括连接到负载的回流闭路。 飞轮二极管放置在回流闭合回路中。 设置成导通/截止电流以驱动负载的MOS晶体管与续流二极管并联连接。 设置电容器将其两端连接到MOS晶体管的栅极和漏极，同时设置电阻器将其两端连接到栅极和MOS晶体管的源极。 在续流二极管的恢复操作期间，借助于电容器和电阻器，MOS晶体管的栅极 - 源极电压在预定时间段内上拉到超过阈值的值。 拉起栅极到源极电压导致续流二极管的软化恢复特性，抑制恢复浪涌。

公开(公告)号：US06287933B1

公开(公告)日：2001-09-11

申请号：US08015268

申请日：1992-01-03

申请人： Makio Iida ,  Shoji Miura ,  Kanemitsu Terada ,  Hiroyuki Ban ,  Kiyoshi Yamamoto ,  Katsuyoshi Oda ,  Yoshihiko Isobe

发明人： Makio Iida ,  Shoji Miura ,  Kanemitsu Terada ,  Hiroyuki Ban ,  Kiyoshi Yamamoto ,  Katsuyoshi Oda ,  Yoshihiko Isobe

IPC分类号： H01L2120

CPC分类号： H01L28/24

摘要： A semiconductor device having a thin film resistor which comprises at least chromium, silicon and nitrogen, and formed on a substrate with having a special ratio of the chemical composition, the semiconductor device having a characteristic such that variations of the resistance value thereof due to temperature variations can be effectively suppressed.

摘要翻译： 一种具有薄膜电阻器的半导体器件，该薄膜电阻器至少包含铬，硅和氮，并且形成在具有特定比例的化学成分的基板上，该半导体器件具有使其由于温度导致的电阻值的变化的特性 可以有效地抑制变化。

公开(公告)号：US06274452B1

公开(公告)日：2001-08-14

申请号：US08965030

申请日：1997-11-05

申请人： Shoji Miura ,  Satoshi Shiraki ,  Hajime Soga

发明人： Shoji Miura ,  Satoshi Shiraki ,  Hajime Soga

IPC分类号： H01L2120

CPC分类号： H01L28/20 ,  H01L21/84 ,  H01L27/13 ,  H01L2924/0002 ,  H01L2924/00

摘要： After an insulating layer made of BPSG is formed on a diffusion layer, a contact hole is formed to expose the diffusion layer. Then, a first aluminum layer is formed in the contact hole. Then, first and second TEOS layers are formed. Thereafter, a thin film resistor is formed on the second TEOS layer by photo-lithography and etching treatments. In this process, the other parts are covered with the second TEOS layer to prevent being damaged. As a result, occurrence of a leak current at the diffusion layer and the like can be prevented. Further, a third TEOS layer is formed on the thin film resistor, and then a second aluminum layer is formed to be electrically connected to the thin film resistor through a contact hole by an ECR dry etching treatment. In this etching treatment, the thin film resistor is not damaged due to the third TEOS layer.

摘要翻译： 在扩散层上形成由BPSG制成的绝缘层之后，形成接触孔以露出扩散层。 然后，在接触孔中形成第一铝层。 然后，形成第一和第二TEOS层。 此后，通过光刻和蚀刻处理在第二TEOS层上形成薄膜电阻器。 在此过程中，其他部分被第二个TEOS层覆盖，以防止损坏。 结果，可以防止在扩散层等处发生泄漏电流。 此外，在薄膜电阻器上形成第三TEOS层，然后通过ECR干蚀刻处理通过接触孔形成第二铝层与薄膜电阻器电连接。 在这种蚀刻处理中，由于第三TEOS层，薄膜电阻器不会被损坏。

公开(公告)号：US5423941A

公开(公告)日：1995-06-13

申请号：US152896

申请日：1993-11-17

申请人： Atsushi Komura ,  Yoshikazu Sakano ,  Kenji Kondo ,  Keiichi Kon ,  Tetsuhiko Sanbei ,  Shoji Miura

发明人： Atsushi Komura ,  Yoshikazu Sakano ,  Kenji Kondo ,  Keiichi Kon ,  Tetsuhiko Sanbei ,  Shoji Miura

IPC分类号： H01L21/302 ,  H01L21/3065 ,  C23F1/00

CPC分类号： H01L21/3065

摘要： A process for forming deep trenches on a surface of a semiconductor substrate by forming a mask on the surface of the semiconductor, which prescribes the position of the trenches; and then dry etching the semiconductor surface using a gas mixture comprising (1) an etchant, bromine containing, gas which etches the semiconductor surface to form trenches, (2) a cleaning, halogen containing, gas which evaporates the residue formed by the etching; and (3) a reactive gas capable of reacting with material formed during the etching and capable of decreasing the wastage of the mask by the etchant gas.

摘要翻译： 一种通过在半导体的表面上形成掩模来形成半导体衬底的表面上的深沟槽的方法，其规定了沟槽的位置; 然后使用气体混合物干燥蚀刻半导体表面，所述气体混合物包括（1）蚀刻剂，含溴的气体，蚀刻半导体表面以形成沟槽，（2）清洁，含卤素的气体，其蒸发由蚀刻形成的残余物; 和（3）能够与在蚀刻期间形成的材料反应的反应气体，并且能够通过蚀刻剂气体减少掩模的浪费。

公开(公告)号：US5284794A

公开(公告)日：1994-02-08

申请号：US960298

申请日：1992-10-13

申请人： Yoshihiko Isobe ,  Makio Iida ,  Shoji Miura ,  Keizou Kajiura ,  Mikimasa Suzuki ,  Masami Saito

发明人： Yoshihiko Isobe ,  Makio Iida ,  Shoji Miura ,  Keizou Kajiura ,  Mikimasa Suzuki ,  Masami Saito

IPC分类号： H01L21/02 ,  H01L21/26

CPC分类号： H01L28/24 ,  H01L28/40 ,  Y10S148/055 ,  Y10S148/136 ,  Y10S438/94

摘要： A semiconductor device has a thin-film resistor trimmed by laser. The semiconductor device comprises a semiconductor substrate having an element region that covers at least part of the surface of the semiconductor substrate, a first insulation film disposed on the surface of the semiconductor substrate, and a second insulation film disposed on the surface of the semiconductor substrate through an opening of the first insulation film. The opening is formed by selectively removing at least part of the first insulation film at a location on the surface of the semiconductor substrate where the element region is not involved. The thin-film resistor is formed on the second insulation film.

摘要翻译： 半导体器件具有通过激光器修整的薄膜电阻器。 半导体器件包括具有覆盖半导体衬底的表面的至少一部分的元件区域的半导体衬底，设置在半导体衬底的表面上的第一绝缘膜和设置在半导体衬底的表面上的第二绝缘膜 通过第一绝缘膜的开口。 通过在不涉及元件区域的半导体衬底的表面上的位置处选择性地去除第一绝缘膜的至少一部分来形成开口。 薄膜电阻器形成在第二绝缘膜上。