公开(公告)号：US06627940B1

公开(公告)日：2003-09-30

申请号：US09937838

申请日：2002-02-05

申请人： Dirk Schumann ,  Bernhard Sell ,  Hans Reisinger ,  Josef Willer

发明人： Dirk Schumann ,  Bernhard Sell ,  Hans Reisinger ,  Josef Willer

IPC分类号： H01L27108

CPC分类号： H01L27/10876 ,  H01L27/10808 ,  H01L27/10823

摘要： A memory-cell array includes a substrate forming parallel first and second trenches. A transistor's upper source/drain region adjoins two of the first and two of the second trenches, and lies above its lower source/drain region. A conductive structure in a first trench associated with the transistor adjoins the upper source/drain region at its first edge. An insulating structure in the associated first trench insulates the conductive structure from a second edge and from a bottom of the associated first trench. A word line, on which is a further insulating layer, is over the upper/source drain region and parallel to the associated first trench bulges into the second trenches. Insulating spaces adjoin the word line laterally. A contact on the conductive structure and in electrical communication with the upper source/drain region connects with a capacitor.

摘要翻译： 存储单元阵列包括形成平行的第一和第二沟槽的衬底。 晶体管的上部源极/漏极区域邻接第一和第二个第二沟槽中的两个，并且位于其下部源极/漏极区域的上方。 与晶体管相关联的第一沟槽中的导电结构在其第一边缘邻接上部源极/漏极区。 相关联的第一沟槽中的绝缘结构将导电结构与相关联的第一沟槽的第二边缘和底部绝缘。 在其上是另一个绝缘层的字线在上部/源极漏极区域上方并且平行于相关联的第一沟槽凸起进入第二沟槽。 绝缘空间横向与字线连接。 导电结构上的与上部源极/漏极区域电连通的触点与电容器连接。

公开(公告)号：US06534362B2

公开(公告)日：2003-03-18

申请号：US10005978

申请日：2001-12-03

申请人： Hans Reisinger

发明人： Hans Reisinger

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A method for fabricating a memory cell configuration, which includes the steps of etching isolation trenches into a semiconductor substrate and thereby forming webs between the isolation trenches and producing bit lines after channel regions have been produced. It furthermore includes performing an etching step which results in the isolation trenches penetrating more deeply into the semiconductor substrate.

公开(公告)号：US5882969A

公开(公告)日：1999-03-16

申请号：US967419

申请日：1997-11-11

申请人： Wolfgang Krautschneider ,  Franz Hofmann ,  Hans Reisinger ,  Josef Willer

发明人： Wolfgang Krautschneider ,  Franz Hofmann ,  Hans Reisinger ,  Josef Willer

IPC分类号： H01L21/822 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L27/11521 ,  H01L21/8221 ,  H01L27/11551

摘要： In a method for manufacturing an electrically writeable and erasable ad-only memory cell arrangement, by self-adjusting process steps, a read-only memory cell arrangement having memory cells that respectively comprise an MOS transistor with a floating gate is manufactured. The MOS transistors are arranged in rows that run parallel. Adjacent rows thus respectively run alternately on the bottom of longitudinal trenches and between adjacent longitudinal trenches. The control gates laterally surround the floating gates so that the memory cells on the bottom of the longitudinal trenches also comprise a coupling ratio>1. A surface requirement per memory cell of 2F.sup.2 (F minimum structural size) is achieved.

摘要翻译： 在通过自调整处理步骤制造电可写和可擦除的仅ad的存储单元布置的方法中，制造了具有分别包括具有浮置栅极的MOS晶体管的存储单元的只读存储单元布置。 MOS晶体管排列成并行的行。 因此，相邻的行分别在纵向沟槽的底部和相邻的纵向沟槽之间交替地行进。 控制门横向围绕浮动栅极，使得纵向沟槽底部的存储单元也包括耦合比> 1。 实现2F2（F最小结构尺寸）每个存储单元的表面要求。