公开(公告)号：US20110203571A1

公开(公告)日：2011-08-25

申请号：US13124677

申请日：2009-10-21

Applicant: Nikolaus Schnetzer ,  Dirk Schumann

Inventor： Nikolaus Schnetzer ,  Dirk Schumann

IPC: F24C3/12 ,  B21D39/00 ,  C25D5/56

CPC classification number: C25D7/00 ,  C25D5/12 ,  C25D5/56 ,  G05G1/10 ,  Y10T428/12535

Abstract: A control element for a household appliance is provided. The control element has a base member made of plastic. The base member has a nickel coating, and a noble metal coating is applied to the nickel coating.

Abstract translation: 提供家用电器的控制元件。 控制元件具有由塑料制成的基座部件。 基底部件具有镍涂层，并且向镍涂层施加贵金属涂层。

公开(公告)号：US07866614B2

公开(公告)日：2011-01-11

申请号：US10988247

申请日：2004-11-12

Applicant: Klaus Erdmann ,  George May ,  Dirk Schumann

Inventor： Klaus Erdmann ,  George May ,  Dirk Schumann

IPC: F16M11/24

CPC classification number: A47L15/4253 ,  D06F39/125 ,  F16M7/00

Abstract: An apparatus for setting the spacing of a free standing range relative to a floor includes a base component for contacting the floor, a threaded element, and a winding follower. The winding follower extends into the helical recess of the threaded element such that the winding follower travels progressively further along the helical recess of the threaded element. A blocking member engages the winding follower during travel of the winding follower along the helical recess of the threaded element to resist a disengagement movement.

公开(公告)号：US07074317B2

公开(公告)日：2006-07-11

申请号：US10436427

申请日：2003-05-12

Applicant: Albert Birner ,  Dirk Schumann ,  Matthias Goldbach

Inventor： Albert Birner ,  Dirk Schumann ,  Matthias Goldbach

IPC: H05K3/07

CPC classification number: H01L21/3063 ,  C25F3/12 ,  H01L27/10861 ,  H01L28/40

Abstract: An electrochemical method is provided for producing trenches for trench capacitors in p-doped silicon with a very high diameter/depth aspect ratio for large scale integrated semiconductor memories. Trenches (macropores) having a diameter of less than about 100 nm and a depth of more than 10 μm can be produced on p-doped silicon having a very low resistivity at a high etching rate.

Abstract translation: 提供电化学方法用于在p掺杂硅中制造用于大规模集成半导体存储器的非常高的直径/深度纵横比的沟槽电容器的沟槽。 可以以高蚀刻速率在具有非常低电阻率的p掺杂硅上产生直径小于约100nm且深度大于10um的沟槽（大孔）。

公开(公告)号：US20060073659A1

公开(公告)日：2006-04-06

申请号：US11285639

申请日：2005-11-22

Applicant: Bernhard Sell ,  Annette Sanger ,  Dirk Schumann

Inventor： Bernhard Sell ,  Annette Sanger ,  Dirk Schumann

IPC: H01L21/8242

CPC classification number: H01L27/10861 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/28518 ,  H01L21/31604 ,  H01L27/10814 ,  H01L28/60

Abstract: The present invention relates to a novel method for fabricating a storage capacitor designed as a trench or a stacked capacitor and is used in particular in a DRAM memory cell. The method includes steps of forming a lower, metallic capacitor electrode, a storage dielectric and an upper capacitor electrode. The lower, metallic capacitor electrode is formed in a self-aligned manner on a silicon base material in such a way that uncovered silicon regions are first produced at locations at which the lower capacitor electrode will be formed, and then metal silicide is selectively formed on the uncovered silicon regions.

Abstract translation: 本发明涉及一种用于制造设计为沟槽或层叠电容器的存储电容器的新颖方法，特别用于DRAM存储单元。 该方法包括形成下部金属电容器电极，存储电介质和上部电容器电极的步骤。 下部金属电容器电极以自对准的方式形成在硅基材上，使得首先在将形成下电容器电极的位置处产生未覆盖的硅区域，然后选择性地形成金属硅化物 未覆盖的硅区域。

公开(公告)号：US06548350B2

公开(公告)日：2003-04-15

申请号：US10093039

申请日：2002-03-07

Applicant: Bernhard Sell ,  Dirk Schumann ,  Josef Willer

Inventor： Bernhard Sell ,  Dirk Schumann ,  Josef Willer

IPC: H01L218242

CPC classification number: H01L28/91 ,  H01L27/10852

Abstract: The capacitor is arranged on the surface of a substrate. A first capacitor electrode has a middle part and a side part, which point vertically upwards, are arranged beside each other and are connected with each other via an upper part located above said middle part and said side part. The middle part is longer than the side part and is connected with other components of the circuit configuration located below said middle part and said side part. The first capacitor electrode is provided with a capacitor dielectric. A second capacitor electrode borders the capacitor dielectric.

公开(公告)号：US08834643B2

公开(公告)日：2014-09-16

申请号：US13259536

申请日：2010-03-22

Applicant: Dirk Schumann ,  Rainer Surkow

Inventor： Dirk Schumann ,  Rainer Surkow

IPC: B08B3/04 ,  C11D3/18 ,  C11D3/20 ,  C11D17/00 ,  C11D3/00 ,  C11D3/32 ,  C11D1/825 ,  C11D1/83

CPC classification number: C11D17/0021 ,  C11D1/825 ,  C11D1/83 ,  C11D3/0052 ,  C11D3/18 ,  C11D3/20 ,  C11D3/201 ,  C11D3/2041 ,  C11D3/2072 ,  C11D3/2093 ,  C11D3/32

Abstract: A method for cleaning objects made of organic or inorganic materials, wherein the relevant material is brought into contact with a composition in the form of a fluid nanophase system, comprising a) at least one water-insoluble substance having a water solubility of less than 4 grams per liter, b) at least one amphiphilic substance (NP-MCA) which has no surfactant structure, is not structure-forming on its own, the solubility of which in water or oil ranges between 4 g and 1000 g per liter and which does not preferably accumulate at the oil-water interface, c) at least one anionic, cationic, amphoteric and/or non-ionic surfactant, d) at least one polar protic solvent, in particular having hydroxy functionality, e) if necessary one or more auxiliary substance.

Abstract translation: 一种用于清洁由有机或无机材料制成的物体的方法，其中所述相关材料与流体纳米相系统形式的组合物接触，所述组合物包含：a）至少一种具有小于4的水溶性的水不溶性物质 克/升，b）至少一种不具有表面活性剂结构的两亲物质（NP-MCA）本身不是结构形成的，其在水或油中的溶解度范围为4g至1000g / l，其中 不优选在油 - 水界面处积聚，c）至少一种阴离子，阳离子，两性和/或非离子表面活性剂，d）至少一种极性质子溶剂，特别是具有羟基官能团，e） 更多辅助物质。

公开(公告)号：US06835612B2

公开(公告)日：2004-12-28

申请号：US10673705

申请日：2003-09-26

Applicant: Annalisa Cappellani ,  Ludwig Dittmar ,  Dirk Schumann

Inventor： Annalisa Cappellani ,  Ludwig Dittmar ,  Dirk Schumann

IPC: H01L21336

CPC classification number: H01L21/28114 ,  H01L21/2652 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28123 ,  H01L21/32137 ,  H01L29/66575

Abstract: A gate layer stack formed with at least two layers is firstly patterned anisotropically and then thelower layer is etched. An isotropic, preferably selective etching step effects a lateral undercutting, i.e. removal of the lower layer as far as the predetermined channel length to form a dimensionally accurate T-gate transistor with a very short channel length.

Abstract translation: 形成有至少两层的栅极层叠层首先被各向异性地图案化，然后蚀刻低温层。 各向同性，优选选择性蚀刻步骤实现横向底切，即将下层除去至预定沟道长度，以形成具有非常短的沟道长度的尺寸精确的T栅极晶体管。

公开(公告)号：USD652988S1

公开(公告)日：2012-01-24

申请号：US29373565

申请日：2011-04-27

Applicant: Dirk Schumann

Designer： Dirk Schumann

公开(公告)号：US20060102815A1

公开(公告)日：2006-05-18

申请号：US10988247

申请日：2004-11-12

Applicant: Klaus Erdmann ,  George May ,  Dirk Schumann

Inventor： Klaus Erdmann ,  George May ,  Dirk Schumann

IPC: F16M11/24

CPC classification number: A47L15/4253 ,  D06F39/125 ,  F16M7/00

Abstract: An apparatus for setting the spacing of a free standing range relative to a floor includes a base component for contacting the floor, a threaded element, and a winding follower. The winding follower extends into the helical recess of the threaded element such that the winding follower travels progressively further along the helical recess of the threaded element. A blocking member engages the winding follower during travel of the winding follower along the helical recess of the threaded element to resist a disengagement movement.

Abstract translation: 用于设定相对于地板的自由站立范围的间隔的装置包括用于接触地板的基座部件，螺纹元件和绕组从动件。 绕组从动件延伸到螺纹元件的螺旋凹槽中，使得绕组从动件沿螺纹元件的螺旋凹槽进一步进一步移动。 在绕线从动件沿着螺纹元件的螺旋凹槽行进期间，阻挡构件接合绕组从动件以抵抗分离运动。

公开(公告)号：US06987295B2

公开(公告)日：2006-01-17

申请号：US10650817

申请日：2003-08-28

Applicant: Bernhard Sell ,  Annette Sänger ,  Dirk Schumann

Inventor： Bernhard Sell ,  Annette Sänger ,  Dirk Schumann

IPC: H01L27/108

CPC classification number: H01L27/10861 ,  H01L27/1203

Abstract: A trench capacitor for use in a DRAM memory cell contains a lower capacitor electrode, a storage dielectric, and an upper capacitor electrode, which are at least partially disposed in a trench. The lower capacitor electrode adjoins, in a lower trench region, a wall of the trench, while in the upper trench region there is a spacer layer that adjoins a wall of the trench and is made from an insulating material. The upper electrode contains at least three layers, a first layer disposed in the trench on the storage dielectric and containing doped polysilicon, a second layer disposed on the first layer and containing metal-silicide, and a third layer disposed on the second layer and containing doped polysilicon. The layers of the upper electrode in each case extending along the walls and the base of the trench up to at least the upper edge of the spacer layer.

Abstract translation: 用于DRAM存储单元的沟槽电容器包括至少部分地设置在沟槽中的下电容器电极，存储电介质和上电容器电极。 下部电容器电极在下部沟槽区域中邻接沟槽的壁，而在上部沟槽区域中存在间隔层，该间隔层邻接沟槽的壁并由绝缘材料制成。 上电极包含至少三层，第一层设置在存储电介质上的沟槽中并含有掺杂多晶硅，第二层设置在第一层上并含有金属硅化物，第三层设置在第二层上并含有 掺杂多晶硅。 每个壳体中的上电极的层沿着沟槽的壁和基底延伸到至少间隔层的上边缘。