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公开(公告)号：US6153483A
公开(公告)日：2000-11-28
申请号：US193005
申请日：1998-11-16
Applicant: Wen-Kuan Yeh , Tony Lin
Inventor： Wen-Kuan Yeh , Tony Lin
IPC: H01L21/266 , H01L21/336 , H01L29/49 , H01L29/78
CPC classification number: H01L29/66598 , H01L21/266 , H01L29/4983 , H01L29/6656 , H01L29/6659 , H01L29/7833
Abstract: A method for manufacturing MOS device that utilizes a special shape spacer as a mask in an ion implantation operation to form a graded source/drain region. The special shaped spacer has a thin wall section on the far side away from the gate so that as ions are implanted into the substrate to form a source/drain region, dopants are implanted to various depths. The graded doping profile in the source/drain region not only reduces the severity of short channel effects, but also forms a base for forming an integral junction over the source/drain region in subsequent self-aligned silicide process.
Abstract translation: 一种用于制造在离子注入操作中利用特殊形状间隔物作为掩模的MOS器件的方法，以形成渐变的源极/漏极区域。 特殊形状的间隔件在远离栅极的远侧具有薄壁部分，使得当离子注入到衬底中以形成源极/漏极区域时，掺杂剂被植入各种深度。 源极/漏极区域中的渐变掺杂分布不仅降低了短沟道效应的严重性，而且还形成了在随后的自对准硅化物工艺中在源极/漏极区域上形成整体结的基极。
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公开(公告)号：US6069061A
公开(公告)日：2000-05-30
申请号：US245648
申请日：1999-02-08
IPC: H01L21/28 , H01L21/336 , H01L29/49
CPC classification number: H01L29/4933 , H01L21/28052 , H01L29/6659
Abstract: A method is provided for forming a polysilicon gate. A stacked gate with a first polysilicon layer/an oxide layer/a second polysilicon layer multiple structure is formed. The invention provides another method for forming a polysilicon gate, in which a first polysilicon layer is formed and waits for a period of time. Then, a second polysilicon layer is formed on the first polysilicon layer. A grain boundary is formed between the first polysilicon layer and the second polysilicon layer. The invention provides still another method for forming a polysilicon gate, in which a polysilicon layer is formed at the temperature of about 600-700.degree. C. and the pressure of about 1-5 torr to form a small-grained polysilicon layer. The three methods for forming a polysilicon gate can prevent the heavy ions from passing through the polysilicon gate and the gate oxide layer into the substrate while performing a pre-amorphization implant process. The absence of these heavy ions in the substrate avoids the subthreshold kink side-effect.
Abstract translation: 提供了形成多晶硅栅极的方法。 形成具有第一多晶硅层/氧化物层/第二多晶硅层多重结构的堆叠栅极。 本发明提供了形成多晶硅栅极的另一种方法，其中形成第一多晶硅层并等待一段时间。 然后，在第一多晶硅层上形成第二多晶硅层。 在第一多晶硅层和第二多晶硅层之间形成晶界。 本发明提供另一种形成多晶硅栅极的方法，其中在约600-700℃的温度和约1-5托的压力下形成多晶硅层以形成小粒度多晶硅层。 用于形成多晶硅栅极的三种方法可以防止重离子在进行预非晶化注入工艺时通过多晶硅栅极和栅极氧化物层进入衬底。 衬底中没有这些重离子避免了亚阈值扭结副作用。
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公开(公告)号：US6057208A
公开(公告)日：2000-05-02
申请号：US057905
申请日：1998-04-09
Applicant: Tony Lin , Heng-Sheng Huang
Inventor： Tony Lin , Heng-Sheng Huang
IPC: H01L21/762 , H01L21/76
CPC classification number: H01L21/76224
Abstract: A method of forming a shallow trench isolation structure is disclosed. A dielectric layer deposited by chemical vapor deposition is used as a sacrificial layer instead of conventional sacrificial oxide layer formed by thermal oxidation. Therefore, the oxide in the trench is further protected and less damaged.
Abstract translation: 公开了形成浅沟槽隔离结构的方法。 通过化学气相沉积沉积的电介质层用作牺牲层，而不是通过热氧化形成的常规牺牲氧化物层。 因此，沟槽中的氧化物被进一步保护并且损坏较少。
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Patent Agency Ranking
公开(公告)号：US6022785A
公开(公告)日：2000-02-08
申请号：US126462
申请日：1998-07-30
Applicant: Wen-Kuan Yeh , Tony Lin
Inventor： Wen-Kuan Yeh , Tony Lin
IPC: H01L21/336 , H01L29/10 , H01L21/425
CPC classification number: H01L29/6659 , H01L29/1083
Abstract: The invention discloses a method of forming a metal-oxide-semiconductor transistor. The method provides a substrate, where a gate structure is formed thereon. Next, a first spacer is formed on the sidewall of the gate structure. A pair of heavily doped regions is formed in the substrate. Then, an annealing process is performed to make the doped ions in the heavily doped regions uniformly distributed. Next, the first spacer is removed and a thin pad dielectric layer is formed over the substrate. Next, a first type halo structure is formed in the bottom portion of the source/drain region beneath the gate structure. A lightly doped region is formed between the gate structure and the first type halo structure and above the first type halo structure. An etching process is performed on the pad dielectric layer to form a second spacer and then the MOS transitor is completed.
Abstract translation: 本发明公开了一种形成金属氧化物半导体晶体管的方法。 该方法提供了其上形成栅极结构的衬底。 接下来，在栅极结构的侧壁上形成第一间隔物。 在衬底中形成一对重掺杂区域。 然后，进行退火处理以使重掺杂区域中的掺杂离子均匀分布。 接下来，去除第一间隔物，并在衬底上形成薄的衬垫介电层。 接下来，在栅极结构下面的源极/漏极区域的底部形成第一类型的晕结构。 在栅极结构和第一类型卤素结构之间并且在第一类型的晕结构之上形成轻掺杂区。 在焊盘电介质层上进行蚀刻处理以形成第二间隔物，然后完成MOS过渡电极。
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公开(公告)号：US5874353A
公开(公告)日：1999-02-23
申请号：US927321
申请日：1997-09-11
Applicant: Tony Lin , Water Lur , Shih-Wei Sun
Inventor： Tony Lin , Water Lur , Shih-Wei Sun
IPC: H01L21/28 , H01L21/336 , H01L29/49 , H01L21/3205 , H01L21/4763
CPC classification number: H01L29/665 , H01L21/28052 , H01L21/28061 , H01L29/4925 , H01L29/4941
Abstract: A method of forming self-aligned silicide devices which includes providing a silicon substrate having shallow trench isolation regions for defining a device area formed therein; then, forming sequentially a gate oxide layer, a polysilicon layer, a first titanium nitride layer, a titanium silicide layer, a second titanium nitride layer and a silicon nitride layer over the substrate. After a gate electrode is etched out from the above layers, a titanium layer is deposited over the device, and then a self-aligned titanium silicide layer is formed using a heating process. The use of a titanium silicide layer having protective top and bottom titanium nitride layers, compared with a single tungsten silicide layer in a conventional method, provides for a self-aligned silicide device having a rather low gate resistance; being free from narrow width effect of a titanium self-aligned silicide layer; is applicable to self-aligned contact window processes, and avoids the cross-diffusion of doped ions in the polysilicon layer of a dual gate electrode having a tungsten polycide layer.
Abstract translation: 一种形成自对准硅化物器件的方法，其包括提供具有浅沟槽隔离区域的硅衬底，用于限定其中形成的器件区域; 然后在衬底上依次形成栅氧化层，多晶硅层，第一氮化钛层，硅化钛层，第二氮化钛层和氮化硅层。 在从上述层蚀刻出栅电极之后，在器件上沉积钛层，然后使用加热工艺形成自对准硅化钛层。 与常规方法中的单个硅化钨层相比，使用具有保护性顶部和底部氮化钛层的硅化钛层提供具有相当低的栅极电阻的自对准硅化物器件; 没有钛自对准硅化物层的窄宽度效应; 适用于自对准接触窗工艺，并避免掺杂离子在具有钨多硅化物层的双栅电极的多晶硅层中的交叉扩散。
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公开(公告)号：US20160365749A1
公开(公告)日：2016-12-15
申请号：US15180836
申请日：2016-06-13
Applicant: Tony Lin
Inventor： Tony Lin
CPC classification number: H02J7/14 , H02J7/0045 , H02J2007/0062
Abstract: A charger is disclosed that is configured with a low profile so as to fit into a charging port of a device that may be in a case or protective housing.
Abstract translation: 公开了一种充电器，其被配置为具有低轮廓以便装配到可以在壳体或保护壳体中的装置的充电端口中。
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