公开(公告)号：US11778814B2

公开(公告)日：2023-10-03

申请号：US17329171

申请日：2021-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Chun-Hsien Lin ,  Sheng-Yuan Hsueh

IPC: H10B20/20 ,  H01L29/423 ,  H10B10/00

CPC classification number: H10B20/20 ,  H01L29/42364 ,  H10B10/18

Abstract: A semiconductor device includes a substrate having an input/output (I/O) region, an one time programmable (OTP) capacitor region, and a core region, a first metal gate disposed on the I/O region, a second metal gate disposed on the core region, and a third metal gate disposed on the OTP capacitor region. Preferably, the first metal gate includes a first high-k dielectric layer, the second metal gate includes a second high-k dielectric layer, and the first high-k dielectric layer and the second high-k dielectric layer include an I-shape.

公开(公告)号：US11705498B2

公开(公告)日：2023-07-18

申请号：US17185985

申请日：2021-02-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/1606 ,  H01L29/45 ,  H01L29/66045 ,  H01L29/78696

Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

公开(公告)号：US11527448B2

公开(公告)日：2022-12-13

申请号：US17134465

申请日：2020-12-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Chi-Mao Hsu ,  Chia-Ming Kuo ,  Guan-Wei Huang ,  Chun-Hsien Lin

IPC: H01L21/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.

公开(公告)号：US20220238677A1

公开(公告)日：2022-07-28

申请号：US17185985

申请日：2021-02-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66

Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

公开(公告)号：US11322600B2

公开(公告)日：2022-05-03

申请号：US16601570

申请日：2019-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/201 ,  H01L29/40 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a first passivation layer adjacent to two sides of the gate electrode, and a p-type semiconductor layer between the gate electrode and the barrier layer. Preferably, a corner of the p-type semiconductor layer contacting a sidewall of the first passivation layer includes a first curve, and a bottom surface of the p-type semiconductor layer directly on the first passivation layer includes a second curve.

公开(公告)号：US20220123200A1

公开(公告)日：2022-04-21

申请号：US17095752

申请日：2020-11-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Chun-Hsien Lin ,  Sheng-Yuan Hsueh

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a first interconnect layer and a second interconnect layer. The first interconnect layer is disposed on the substrate, and the first interconnect layer includes a first dielectric layer around a plurality of first magnetic tunneling junction (MTJ) structures. The second interconnect layer is disposed on the first interconnect layer, and the second interconnect layer includes a second dielectric layer around a plurality of second MTJ structures, wherein, the second MTJ structures and the first MTJ structures are alternately arranged along a direction. The semiconductor device may obtain a reduced size of each bit cell under a permissible process window, so as to improve the integration of components.

公开(公告)号：US20210391339A1

公开(公告)日：2021-12-16

申请号：US16923117

申请日：2020-07-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chun-Hsien Lin ,  Chien-Hung Chen

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L21/285 ,  H01L21/8238

Abstract: A method for fabricating a static random access memory (SRAM) includes the steps of: forming a gate structure on a substrate; forming an epitaxial layer adjacent to the gate structure; forming a first interlayer dielectric (ILD) layer around the gate structure; transforming the gate structure into a metal gate; forming a contact hole exposing the epitaxial layer, forming a barrier layer in the contact hole, forming a metal layer on the barrier layer, and then planarizing the metal layer and the barrier layer to form a contact plug. Preferably, a bottom portion of the barrier layer includes a titanium rich portion and a top portion of the barrier layer includes a nitrogen rich portion.

公开(公告)号：US20210210675A1

公开(公告)日：2021-07-08

申请号：US17209251

申请日：2021-03-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an inter-metal dielectric (IMD) layer on the substrate, a MTJ in the IMD layer on the MTJ region, a first metal interconnection in the IMD layer on the logic region, and protrusions adjacent to two sides of the first metal interconnection. Preferably, the MTJ further includes a bottom electrode, a fixed layer, a barrier layer, a free layer, and a top electrode.

公开(公告)号：US20210083073A1

公开(公告)日：2021-03-18

申请号：US16601570

申请日：2019-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/201 ,  H01L29/40 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a first passivation layer adjacent to two sides of the gate electrode, and a p-type semiconductor layer between the gate electrode and the barrier layer. Preferably, a corner of the p-type semiconductor layer contacting a sidewall of the first passivation layer includes a first curve, and a bottom surface of the p-type semiconductor layer directly on the first passivation layer includes a second curve.

公开(公告)号：US20210057551A1

公开(公告)日：2021-02-25

申请号：US17090902

申请日：2020-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chang Lin ,  Bo-Han Huang ,  Chih-Chung Chen ,  Chun-Hsien Lin ,  Shih-Hung Tsai ,  Po-Kuang Hsieh

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/51

Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.