公开(公告)号：US09343376B1

公开(公告)日：2016-05-17

申请号：US14872162

申请日：2015-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L21/00 ,  H01L21/84 ,  H01L29/06 ,  H01L21/02 ,  H01L29/78 ,  H01L21/308 ,  H01L21/265 ,  H01L29/423

CPC classification number: H01L21/84 ,  B82Y10/00 ,  H01L21/02603 ,  H01L21/26506 ,  H01L21/3086 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7842 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device includes following steps. First of all, a first nanowire structure and a second nanowire structure are formed on a substrate. Next, a compressive stress layer is formed on the first nanowire structure, and the first nanowire structure is driven to a compressive nanowire structure. Then, a tensile stress layer is formed on the second nanowire structure, and the second nanowire structure is driven into a tensile nanowire structure.

Abstract translation: 制造半导体器件的方法包括以下步骤。 首先，在基板上形成第一纳米线结构和第二纳米线结构。 接下来，在第一纳米线结构上形成压应力层，将第一纳米线结构驱动为压缩纳米线结构。 然后，在第二纳米线结构上形成拉伸应力层，将第二纳米线结构驱动成拉伸纳米线结构。

公开(公告)号：US12268028B2

公开(公告)日：2025-04-01

申请号：US18395616

申请日：2023-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H10D64/01 ,  H10D30/01 ,  H10D30/47 ,  H10D62/10 ,  H10D64/23

Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate is provided. A semiconductor channel layer is formed on the substrate. A semiconductor barrier layer is formed on the semiconductor channel layer. An etching process is performed to expose a portion of the semiconductor channel layer. A dielectric layer is formed to cover the semiconductor barrier layer and the exposed semiconductor channel layer. A first electrode is formed after forming the dielectric layer, where the first electrode includes a body portion and a vertical extension portion, the body portion is electrically connected to the semiconductor barrier layer, and a bottom surface of the vertical extension portion is lower than a top surface of the semiconductor channel layer.

公开(公告)号：US20250081495A1

公开(公告)日：2025-03-06

申请号：US18948430

申请日：2024-11-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

Abstract: A high electron mobility transistor includes a substrate, a buffer layer on the substrate, a channel layer on the buffer layer, a barrier layer on the channel layer, a semiconductor gate layer on the barrier layer, a metal gate layer on the semiconductor gate layer, and a gate electrode on the metal gate layer. The gate electrode includes a first portion in direct contact with the metal gate layer and having a first width, a second portion on the first portion and having a second width, and a third portion on the second portion and having a third width. The third width is larger than the second width. The second width is larger than the first width.

公开(公告)号：US20250072026A1

公开(公告)日：2025-02-27

申请号：US18946849

申请日：2024-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L29/778

Abstract: An HEMT with a stair-like compound layer as a drain includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A source electrode, a gate electrode and a drain electrode are disposed on the second III-V compound layer. The gate electrode is disposed between the source electrode and the drain electrode. A first P-type III-V compound layer is disposed between the drain electrode and the second III-V compound layer. The first P-type III-V compound layer is stair-like.

公开(公告)号：US12154958B2

公开(公告)日：2024-11-26

申请号：US18132435

申请日：2023-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/792

Abstract: A semiconductor structure includes a substrate, an insulating layer disposed on the substrate, an active layer disposed on the insulating layer, a plurality of isolation structures in the active layer to define a first device region and a non-device region of the active layer, a first semiconductor device formed on the first device region of the active layer, and a charge trap structure extending through the non-device region of the active layer. In a plane view, the charge trap structure and the non-device region form concentric closed ring surrounding the first device region.

公开(公告)号：US20240387720A1

公开(公告)日：2024-11-21

申请号：US18788160

申请日：2024-07-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/66

Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of first forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a compressive stress layer adjacent to one side of the p-type semiconductor layer, and then forming a tensile stress layer adjacent to another side of the p-type semiconductor layer.

公开(公告)号：US12080787B2

公开(公告)日：2024-09-03

申请号：US17671549

申请日：2022-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/0217 ,  H01L29/66462

Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of first forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a compressive stress layer adjacent to one side of the p-type semiconductor layer, and then forming a tensile stress layer adjacent to another side of the p-type semiconductor layer.

公开(公告)号：US20240258417A1

公开(公告)日：2024-08-01

申请号：US18631091

申请日：2024-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/66462

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate capping layer, a dielectric layer, and a gate electrode. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate capping layer is disposed on the semiconductor barrier layer, and the dielectric layer conformally covers the gate capping layer and surrounds the periphery of the gate capping layer. The gate electrode is disposed on the dielectric layer and covers at least one sidewall of the gate capping layer.

公开(公告)号：US20240097004A1

公开(公告)日：2024-03-21

申请号：US17965803

申请日：2022-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/778

CPC classification number: H01L29/66431 ,  H01L29/41725 ,  H01L29/7786

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a gate structure on the barrier layer, a gate spacer on the gate structure, and a gate contact on the gate spacer. The gate contact includes a first portion and a second portion respectively at two sides of the gate spacer and directly contacting the gate structure.

公开(公告)号：US11894453B2

公开(公告)日：2024-02-06

申请号：US17897217

申请日：2022-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/205 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L21/0254 ,  H01L21/02639 ,  H01L29/205 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66462

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a gate dielectric layer on the barrier layer; forming a work function metal layer on the gate dielectric layer; patterning the work function metal layer and the gate dielectric layer; forming a gate electrode on the work function metal layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.