公开(公告)号：US20220004420A1

公开(公告)日：2022-01-06

申请号：US17476090

申请日：2021-09-15

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Cyprien Laplace ,  Regis Duchesne ,  Ye Li ,  Alexander Fainkichen

IPC: G06F9/455 ,  G06F11/34 ,  G06F1/3287 ,  G06F1/3234 ,  G06F9/50 ,  G06F11/30

Abstract: Techniques for optimizing CPU usage in a host system based on VM guest OS power and performance management are provided. In one embodiment, a hypervisor of the host system can capture information from a VM guest OS that pertains to a target power or performance state set by the guest OS for a vCPU of the VM. The hypervisor can then perform, based on the captured information, one or more actions that align usage of host CPU resources by the vCPU with the target power or performance state.

公开(公告)号：US11169838B2

公开(公告)日：2021-11-09

申请号：US16744351

申请日：2020-01-16

Applicant: VMware, Inc.

Inventor： Cyprien Laplace ,  Regis Duchesne ,  Andrei Warkentin ,  Ye Li ,  Alexander Fainkichen

IPC: G06F9/455

Abstract: An example method of interfacing with a hypervisor in a computing system is described. The computing system includes a processor having at least three hierarchical privilege levels including a third privilege level more privileged than a second privilege level, the second privilege level more privileged than a first privilege level. The method includes configuring, by the hypervisor executing at the third privilege level, the processor to trap reads to a debug communication channel (DCC) status register of the processor to the third privilege level; trapping, at the hypervisor, a read to the DCC status register by guest software executing in a virtual machine (VM) managed by the hypervisor, the guest software executing at the first or second privilege level; reading, at the hypervisor, a plurality of registers of the processor to obtain data stored by the guest software; and returning execution from the hypervisor to the guest software.

公开(公告)号：US10552172B2

公开(公告)日：2020-02-04

申请号：US15880964

申请日：2018-01-26

Applicant: VMware, Inc.

Inventor： Ye Li ,  Cyprien Laplace ,  Andrei Warkentin ,  Alexander Fainkichen ,  Regis Duchesne

IPC: G06F9/44 ,  G06F9/455 ,  G06F16/11 ,  G06F9/4401 ,  G06F9/445

Abstract: An example method of provisioning a virtual appliance to a virtualized computing system, comprising: deploying the virtual appliance to the virtualized computing system, the virtual appliance including a system partition, one or more disk images, and configuration data, the configuration data defining a virtual machine executable on each of a plurality of processor architectures, the system partition configured to boot on any one of the plurality of processor architectures; and booting the virtual appliance from the system partition.

公开(公告)号：US10185664B1

公开(公告)日：2019-01-22

申请号：US15639800

申请日：2017-06-30

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Cyprien Laplace ,  Regis Duchesne ,  Alexander Fainkichen ,  Ye Li

IPC: G06F9/4401 ,  G06F12/1027 ,  G06F12/1009 ,  G06F9/445

Abstract: A method of re-mapping a boot loader image from a first to a second address space includes: determining a difference in a virtual address of the boot loader image in the first and second address spaces; building page tables for a third address space that maps a code section within the boot loader image at first and second address ranges separated by the difference and the code section causes execution to jump from a first instruction in the first address range to a second instruction in the second address range; executing an instruction of the code section in the first address space using pages tables for the first address space; executing the first instruction and then the second instruction using the page tables for the third address space; and executing an instruction of the boot loader image in the second address space using page tables for the second address space.

公开(公告)号：US10067784B2

公开(公告)日：2018-09-04

申请号：US15184455

申请日：2016-06-16

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Harvey Tuch ,  Cyprien Laplace ,  Alexander Fainkichen

IPC: G06F9/455 ,  G06F9/38 ,  G06F11/36 ,  G06F13/24 ,  G06F9/48

Abstract: A method of providing a backdoor interface between software executing in a virtual machine and a hypervisor executing on a computing system that supports the virtual machine includes trapping, at the hypervisor, an exception generated in response to execution of a debug instruction on a central processing unit (CPU) by the software; identifying, by an exception handler of the hypervisor handling the exception, an equivalence between an immediate operand of the debug instruction and a predefined value; and invoking, in response to the equivalence, a backdoor service of the hypervisor using state of at least one register of the CPU as parametric input, the state being set by the software prior to executing the debug instruction.

公开(公告)号：US10002084B1

公开(公告)日：2018-06-19

申请号：US15383572

申请日：2016-12-19

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Cyprien Laplace ,  Ye Li

IPC: G06F12/14 ,  G06F12/1027 ,  G06F9/455 ,  G06F12/1009

Abstract: An example method of memory management in a virtualized computing system includes: generating a page table hierarchy that includes address translations to first pages of memory that store kernel software and second pages of the memory that store user software; configuring a processor to: 1) implement a first address translation scheme, which uses a first virtual address width, for a hypervisor privilege level; 2) implement a second address translation scheme, which uses a second virtual address width, for supervisor and user privilege levels, where the first virtual address width is larger than the second virtual address width; and 3) use the page table hierarchy for each of the first and second address translation schemes; and executing the kernel software at the hypervisor privilege level and the user software at the user privilege level.

公开(公告)号：US20160378543A1

公开(公告)日：2016-12-29

申请号：US14876831

申请日：2015-10-07

Applicant: VMWARE, INC.

Inventor： ANDREI WARKENTIN ,  Irfan Ulla Khan ,  Cyprien Laplace ,  Harvey Tuch ,  Alexander Fainkichen

IPC: G06F9/48 ,  G06F13/26

CPC classification number: G06F9/4818 ,  G06F13/26

Abstract: A method is provided for handling interrupts in a processor, the interrupts including regular interrupts having a range of priorities and a pseudo non-maskable interrupt (PNMI) that is of a higher priority than any of the regular interrupts. The method includes the steps of obtaining an interrupt vector corresponding to a received interrupt, and if the received interrupt is a regular interrupt, enabling interrupts in the processor so that a PNMI can be received while handling the regular interrupt, executing a regular interrupt handler using the interrupt vector, and disabling interrupts in the processor. On the other hand, if the received interrupt is a PNMI, a PNMI interrupt handler is executed using the interrupt vector as an input thereto.

Abstract translation: 提供了一种用于处理处理器中断的方法，所述中断包括具有优先级范围的规则中断和比任何常规中断更高优先级的伪不可屏蔽中断（PNMI）。 该方法包括获得与接收到的中断相对应的中断向量的步骤，并且如果接收到的中断是常规中断，则允许处理器中的中断，使得在处理常规中断时可以接收PNMI，执行常规中断处理程序使用 中断向量和禁用处理器中断。 另一方面，如果接收到的中断是PNMI，则使用中断向量作为其输入来执行PNMI中断处理程序。