公开(公告)号：US11550609B2

公开(公告)日：2023-01-10

申请号：US16744356

申请日：2020-01-16

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Cyprien Laplace ,  Regis Duchesne ,  Alexander Fainkichen ,  Shruthi Muralidhara Hiriyuru ,  Ye Li

IPC: G06F9/455

Abstract: An example method of interfacing with a hypervisor in a computing system is described, which includes a processor having at least three hierarchical privilege levels including a third privilege level more privileged than a second privilege level, the second privilege level more privileged than a first privilege level. The method includes: identifying an input/output (I/O) space instruction, not supported by the processor, to be performed for backdoor communication between the hypervisor and guest software executing in a virtual machine (VM) managed by the hypervisor, the hypervisor executing at the third privilege level; writing one or more parameters to one or more registers of the processor that are mapped to one or more unsupported registers used by the I/O space instruction; writing a value indicative of the I/O space instruction to a designated register of the processor; executing an instruction, by the guest software executing at the first or second privilege level, which is trapped to the third privilege level.

公开(公告)号：US10282226B2

公开(公告)日：2019-05-07

申请号：US15385568

申请日：2016-12-20

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Cyprien Laplace ,  Regis Duchesne ,  Ye Li ,  Alexander Fainkichen

IPC: G06F1/32 ,  G06F9/455 ,  G06F11/34 ,  G06F1/3287 ,  G06F1/3234 ,  G06F9/50

Abstract: Techniques for optimizing CPU usage in a host system based on VM guest OS power and performance management are provided. In one embodiment, a hypervisor of the host system can capture information from a VM guest OS that pertains to a target power or performance state set by the guest OS for a vCPU of the VM. The hypervisor can then perform, based on the captured information, one or more actions that align usage of host CPU resources by the vCPU with the target power or performance state.

公开(公告)号：US20180173553A1

公开(公告)日：2018-06-21

申请号：US15385568

申请日：2016-12-20

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Cyprien Laplace ,  Regis Duchesne ,  Ye Li ,  Alexander Fainkichen

IPC: G06F9/455 ,  G06F11/34 ,  G06F1/32 ,  G06F9/48

CPC classification number: G06F9/45558 ,  G06F1/3234 ,  G06F1/3287 ,  G06F9/5077 ,  G06F11/3423

Abstract: Techniques for optimizing CPU usage in a host system based on VM guest OS power and performance management are provided. In one embodiment, a hypervisor of the host system can capture information from a VM guest OS that pertains to a target power or performance state set by the guest OS for a vCPU of the VM. The hypervisor can then perform, based on the captured information, one or more actions that align usage of host CPU resources by the vCPU with the target power or performance state.

公开(公告)号：US12248799B2

公开(公告)日：2025-03-11

申请号：US17553607

申请日：2021-12-16

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Ye Li ,  Alexander Fainkichen ,  Regis Duchesne ,  Cyprien Laplace ,  Shruthi Muralidhara Hiriyuru ,  Sunil Kumar Kotian

IPC: G06F9/455

Abstract: An example method of managing guest time for a virtual machine (VM) supported by a hypervisor of a virtualized host computer includes: configuring, by the hypervisor, a central processing unit (CPU) of the host computer to trap, to the hypervisor, access by guest code in the VM to a physical counter and timer of the CPU; configuring, by the hypervisor, the guest code in the VM to use the physical counter and timer of the CPU rather than a virtual counter and timer of the CPU; trapping, at the hypervisor, an access to the physical counter and timer by the guest code; and executing, by the hypervisor, the access to the physical counter and timer on behalf of the guest code while compensating for an adjustment of a system count of the physical counter and timer to maintain the guest time as scaled with respect to frequency of the physical counter and timer.

公开(公告)号：US11263019B2

公开(公告)日：2022-03-01

申请号：US16521434

申请日：2019-07-24

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Cyprien Laplace ,  Ye Li ,  Alexander Fainkichen ,  Regis Duchesne

IPC: G06F15/177 ,  G06F9/00 ,  G06F9/4401 ,  G06F16/22

Abstract: A method for generating boot tables for a device having access to device information. It is determined whether there exists at least one system boot table stored in a memory. If it is determined that a system boot table does not exist, the device information is retrieved, and the device information is converted to at least one boot table. The converting includes generating a first boot table by populating the first boot table with information of components of the device that have a correspondence to a computer system boot information standard. The generating also includes generating a second boot table for another component of the device that does not have a correspondence to the computer system boot information standard, by creating an entry in the second boot table that is populated with an identifier used to find a compatible component defined in the computer system boot standard.

公开(公告)号：US10698783B2

公开(公告)日：2020-06-30

申请号：US15865770

申请日：2018-01-09

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Cyprien Laplace ,  Regis Duchesne ,  Ye Li ,  Alexander Fainkichen

IPC: G06F9/455 ,  G06F11/30 ,  G06F13/10

Abstract: A method of detecting virtualization in a computing system, which includes a processor having at least three hierarchical privilege levels including a third privilege level more privileged than a second privilege level, the second privilege level more privileged than a first privilege level, is described. The method includes: executing a program on the processor at a privilege level less privileged than the third privilege level, the program including a load-exclusive instruction of the processor, followed by at least one instruction of the processor capable of being trapped to the third privilege level, followed by a store-exclusive instruction of the processor; and determining presence or absence of virtualization software at least a portion of which executes at the third privilege level in response to a return status of the store-exclusive instruction.

公开(公告)号：US10379870B2

公开(公告)日：2019-08-13

申请号：US15644670

申请日：2017-07-07

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Cyprien Laplace ,  Regis Duchesne ,  Alexander Fainkichen ,  Ye Li

IPC: G06F9/44 ,  G06F9/4401 ,  G06F3/06 ,  G06F12/1009 ,  G06F9/38 ,  G06F12/121 ,  G06F12/1027

Abstract: A method of initializing a secondary processor pursuant to a soft reboot of system software comprises storing code to be executed by the secondary processor in memory, building first page tables to map the code into a first address space and second page tables to identically map the code into a second address space, fetching a first instruction of the code based on a first virtual address in the first address space and the first page tables, and executing the code beginning with the first instruction to switch from the first to the second page tables. The method further comprises, fetching a next instruction of the code using a second virtual address, which is identically mapped to a corresponding machine address, turning off a memory management unit of the secondary processor, and executing a waiting loop until a predetermined location in the physical memory changes in value.

公开(公告)号：US20180173539A1

公开(公告)日：2018-06-21

申请号：US15387332

申请日：2016-12-21

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Cyrien Laplace ,  Alexander Fainkichen ,  Ye Li ,  Regis Duchesne

IPC: G06F9/44 ,  G06F12/1009

CPC classification number: G06F12/1009 ,  G06F9/4401 ,  G06F12/109 ,  G06F12/1441 ,  G06F2212/1008 ,  G06F2212/657

Abstract: Examples construct a bootloader address space using a page fault exception. A bootloader executing in machine address (MA) space determines the MA at which the bootloader has been loaded into memory. The bootloader calculates a difference between an expected virtual address (VA) and the loaded MA. The bootloader defines a page table mapping the bootloader MA to an expected VA, and sets an exception handling vector to point to the expected VA. When a memory management unit (MMU) utilizing the defined page table for address translation is enabled, a page fault exception occurs. The page fault exception handling resumes execution of the bootloader at the expected VA via an exception handling vector pointing thereto.

公开(公告)号：US12118362B2

公开(公告)日：2024-10-15

申请号：US17559346

申请日：2021-12-22

Applicant: VMware, Inc.

Inventor： Cyprien Laplace ,  Sunil Kumar Kotian ,  Andrei Warkentin ,  Regis Duchesne ,  Alexander Fainkichen ,  Shruthi Muralidhara Hiriyuru ,  Ye Li

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/455

CPC classification number: G06F9/3861 ,  G06F9/45558

Abstract: An example method of exception handling in a computer system is described. The computer system includes a physical central processing unit (PCPU) and a system memory, the system memory storing a first stack, a second stack, and a double fault stack associated with the PCPU. The method includes: storing, by an exception handler executing in the computer system, an exception frame on the double fault stack in response to a stack overflow condition of the first stack; switching, by the exception handler, a first stack pointer of the PCPU from pointing to the first stack to pointing to the double fault stack; setting a current stack pointer of the PCPU to the first stack pointer; and executing software on the PCPU with the current stack pointer pointing to the double fault stack.

公开(公告)号：US11561894B2

公开(公告)日：2023-01-24

申请号：US17142980

申请日：2021-01-06

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Alexander Fainkichen ,  Ye Li ,  Regis Duchesne ,  Cyprien Laplace ,  Shruthi Hiriyuru ,  Sunil Kotian

IPC: G06F12/06 ,  G06F9/455 ,  G06F13/16 ,  G06F13/42

Abstract: Techniques for enabling efficient guest OS access to PCIe configuration space are provided. In one set of embodiments, a hypervisor can reserve a single host physical memory page in the host physical memory of a host system and can populate the single host physical memory page with a value indicating non-presence of PCIe device functions. The hypervisor can then create, for each guest physical memory page in a guest physical memory of a virtual machine (VM) corresponding to a PCIe configuration space of an absent PCIe device function in the VM, a mapping in the hypervisor's second-level page tables that maps the guest physical memory page to the single host physical memory page.