中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

35 records (took 0.017 seconds)

    Unified hypercall interface across processors in virtualized computing systems
    1.
    发明授权
    Unified hypercall interface across processors in virtualized computing systems 有权

    公开(公告)号：US11550609B2

    公开(公告)日：2023-01-10

    申请号：US16744356

    申请日：2020-01-16

    Applicant: VMware, Inc.

    Inventor： Andrei Warkentin ,  Cyprien Laplace ,  Regis Duchesne ,  Alexander Fainkichen ,  Shruthi Muralidhara Hiriyuru ,  Ye Li

    IPC: G06F9/455

    Abstract: An example method of interfacing with a hypervisor in a computing system is described, which includes a processor having at least three hierarchical privilege levels including a third privilege level more privileged than a second privilege level, the second privilege level more privileged than a first privilege level. The method includes: identifying an input/output (I/O) space instruction, not supported by the processor, to be performed for backdoor communication between the hypervisor and guest software executing in a virtual machine (VM) managed by the hypervisor, the hypervisor executing at the third privilege level; writing one or more parameters to one or more registers of the processor that are mapped to one or more unsupported registers used by the I/O space instruction; writing a value indicative of the I/O space instruction to a designated register of the processor; executing an instruction, by the guest software executing at the first or second privilege level, which is trapped to the third privilege level.

    Deploying enclaves on different tee backends using a universal enclave binary
    4.
    发明授权
    Deploying enclaves on different tee backends using a universal enclave binary 有权

    公开(公告)号：US12147530B2

    公开(公告)日：2024-11-19

    申请号：US17960738

    申请日：2022-10-05

    Applicant: VMware, Inc.

    Inventor： Ye Li ,  Anoop Jaishankar ,  John Manferdelli ,  David Ott ,  Andrei Warkentin

    IPC: G06F21/53 ,  G06F21/12 ,  G06F21/54

    Abstract: The disclosure herein describes deploying a Virtual Secure Enclave (VSE) using a universal enclave binary and a Trusted Runtime (TR). A universal enclave binary is generated that includes a set of binaries of Instruction Set Architectures (ISAs) associated with Trusted Execution Environment (TEE) hardware backends. A TEE hardware backend is identified in association with a VSE-compatible device. A VSE that is compatible with the identified TEE hardware backend is generated on the VSE-compatible device and an ISA binary that matches the TEE hardware backend is selected from the universal enclave binary. The selected binary is linked to a runtime library of the TR and loads the linked binary into memory of the generated VSE. The execution of a trusted application is initiated in the generated VSE using a set of interfaces of the TR. The trusted application depends on the TR interfaces rather than the selected ISA binary.

    POWER EFFICIENT MEMORY VALUE UPDATES FOR ARM ARCHITECTURES
    6.
    发明公开
    POWER EFFICIENT MEMORY VALUE UPDATES FOR ARM ARCHITECTURES 审中-公开

    公开(公告)号：US20230237010A1

    公开(公告)日：2023-07-27

    申请号：US17580866

    申请日：2022-01-21

    Applicant: VMware, Inc.

    Inventor： Regis Duchesne ,  Andrei Warkentin ,  Cyprien Laplace ,  Ye Li ,  Alexander Fainkichen ,  Shruthi Hiriyuru ,  Sunil Kotian

    IPC: G06F15/78 ,  G06F9/30

    CPC classification number: G06F15/7842 ,  G06F9/30123

    Abstract: Disclosed are various examples of providing provide efficient waiting for detection of memory value updates for Advanced RISC Machines (ARM) architectures. An ARM processor component instructs a memory agent to perform a processing action, and executes a waiting function. The waiting function ensures that the processing action is completed by the memory agent. The waiting function performs an exclusive load at a memory location, and a wait for event (WFE) instruction that causes the ARM processor component to wait in a low-power mode for an event register to be set. Once the event register is set, the waiting function completes and a second processing action is executed by the ARM processor component.

    Non-unified cache coherency maintenance for virtual machines
    10.
    发明授权
    Non-unified cache coherency maintenance for virtual machines 有权

    公开(公告)号：US11210222B2

    公开(公告)日：2021-12-28

    申请号：US15878062

    申请日：2018-01-23

    Applicant: VMware, Inc.

    Inventor： Ye Li ,  Cyprien Laplace ,  Andrei Warkentin ,  Alexander Fainkichen ,  Regis Duchesne

    IPC: G06F12/0815 ,  G06F12/0808

    Abstract: An example method of maintaining cache coherency in a virtualized computing system includes: trapping access to a memory page by guest software in a virtual machine at a hypervisor managing the virtual machine, where the memory page is not mapped in a second stage page table managed by the hypervisor; performing cache coherency maintenance for instruction and data caches of a central processing unit (CPU) in the virtualized computing system in response to the trap; mapping the memory page in the second stage page table with execute permission; and resuming execution of the virtual machine.

Patent Agency Ranking