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41.发明申请Auto-Ordering of Strongly Ordered, Device, and Exclusive Transactions Across Multiple Memory Regions 有权在多个内存区域自动排序强顺序，设备和独占交易公开(公告)号：US20130151799A1
公开(公告)日：2013-06-13
申请号：US13315370
申请日：2011-12-09
申请人： Jason Lawrence Panavich , James Norris Dieffenderfer , Thomas Andrew Sartorius , Thomas Philip Speier
发明人： Jason Lawrence Panavich , James Norris Dieffenderfer , Thomas Andrew Sartorius , Thomas Philip Speier
IPC分类号： G06F12/00
CPC分类号： G06F13/1621
摘要： Efficient techniques are described for controlling ordered accesses in a weakly ordered storage system. A stream of memory requests is split into two or more streams of memory requests and a memory access counter is incremented for each memory request. A memory request requiring ordered memory accesses is identified in one of the two or more streams of memory requests. The memory request requiring ordered memory accesses is stalled upon determining a previous memory request from a different stream of memory requests is pending. The memory access counter is decremented for each memory request guaranteed to complete. A count value in the memory access counter that is different from an initialized state of the memory access counter indicates there are pending memory requests. The memory request requiring ordered memory accesses is processed upon determining there are no further pending memory requests.
摘要翻译： 描述了用于控制弱订单存储系统中有序访问的高效技术。 存储器请求流被分成两个或更多个存储器请求流，并且每个存储器请求增加存储器访问计数器。 需要有序存储器访问的存储器请求在两个或更多个存储器请求流中的一个中被识别。 在从不同的存储器请求流确定先前的存储器请求正在等待时，需要有序存储器访问的存储器请求被停止。 对于保证完成的每个存储器请求，存储器访问计数器递减。 与存储器访问计数器的初始化状态不同的存储器访问计数器中的计数值指示存在未决存储器请求。 在确定没有进一步的未决存储器请求时，处理需要有序存储器访问的存储器请求。
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42.发明申请公开(公告)号：US20120059995A1
公开(公告)日：2012-03-08
申请号：US13292651
申请日：2011-11-09
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/128 , G06F2212/1028 , Y02D10/13
摘要： Techniques and methods are used to reduce allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby castouts are reduced. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information. Preventing an allocation of the selected line saves power that would be associated with the allocation.
摘要翻译： 技术和方法用于减少从较低级别缓存中移位的高速缓存行的更高级缓存的分配。 对于在下一级高速缓存中被确定为冗余的移位高速缓存线，防止移位的高速缓存行的分配，从而减少了突发。 为此，选择在下一级缓存中移位的行。 识别与所选行相关联的信息，其指示所选择的行存在于较高级别的高速缓存中。 基于所识别的信息来防止在较高级别高速缓存中的所选行的分配。 防止所选线路的分配节省与分配相关联的功率。
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43.发明授权Auto-ordering of strongly ordered, device, and exclusive transactions across multiple memory regions 有权自动排序多个内存区域的强有序，设备和独占事务公开(公告)号：US08782356B2
公开(公告)日：2014-07-15
申请号：US13315370
申请日：2011-12-09
申请人： Jason Lawrence Panavich , James Norris Dieffenderfer , Thomas Andrew Sartorius , Thomas Philip Speier
发明人： Jason Lawrence Panavich , James Norris Dieffenderfer , Thomas Andrew Sartorius , Thomas Philip Speier
CPC分类号： G06F13/1621
摘要： Efficient techniques are described for controlling ordered accesses in a weakly ordered storage system. A stream of memory requests is split into two or more streams of memory requests and a memory access counter is incremented for each memory request. A memory request requiring ordered memory accesses is identified in one of the two or more streams of memory requests. The memory request requiring ordered memory accesses is stalled upon determining a previous memory request from a different stream of memory requests is pending. The memory access counter is decremented for each memory request guaranteed to complete. A count value in the memory access counter that is different from an initialized state of the memory access counter indicates there are pending memory requests. The memory request requiring ordered memory accesses is processed upon determining there are no further pending memory requests.
摘要翻译： 描述了用于控制弱订单存储系统中有序访问的高效技术。 存储器请求流被分成两个或更多个存储器请求流，并且每个存储器请求增加存储器访问计数器。 需要有序存储器访问的存储器请求在两个或更多个存储器请求流中的一个中被识别。 在从不同的存储器请求流确定先前的存储器请求正在等待时，需要有序存储器访问的存储器请求被停止。 对于保证完成的每个存储器请求，存储器访问计数器递减。 与存储器访问计数器的初始化状态不同的存储器访问计数器中的计数值指示存在未决存储器请求。 在确定没有进一步的未决存储器请求时，处理需要有序存储器访问的存储器请求。
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44.发明授权公开(公告)号：US08386716B2
公开(公告)日：2013-02-26
申请号：US13292651
申请日：2011-11-09
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/128 , G06F2212/1028 , Y02D10/13
摘要： Techniques and methods are used to control allocations of cache lines to a higher level cache that have been displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby the displaced cache line castouts are not allocated to the higher level cache. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information.
摘要翻译： 技术和方法用于控制高速缓存行分配到从较低级别缓存中移位的更高级缓存。 对于在下一级高速缓存中被确定为冗余的移位高速缓存线，防止移位的高速缓存线的分配，由此不移位的高速缓存行突发不被分配给更高级的高速缓存。 为此，选择在下一级缓存中移位的行。 识别与所选行相关联的信息，其指示所选择的行存在于较高级别的高速缓存中。 基于所识别的信息来防止在较高级别高速缓存中的所选行的分配。
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45.发明授权公开(公告)号：US06985972B2
公开(公告)日：2006-01-10
申请号：US10264163
申请日：2002-10-03
申请人： James Norris Dieffenderfer , Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Barry Joe Wolford
发明人： James Norris Dieffenderfer , Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Barry Joe Wolford
CPC分类号： G06F13/366 , G06F12/0831 , G06F2212/1028 , G06F2213/0038 , Y02D10/13 , Y02D10/14
摘要： A data processing system with a snooper that is capable of dynamically enabling and disabling its snooping capabilities (i.e., snoop detect and response). The snooper is connected to a bus controller via a plurality of interconnects, including a snooperPresent signal, a snoop response signal and a snoop detect signal. When the snooperPresent signal is asserted, subsequent snoop requests are sent to the snooper, and the snooper is polled for a snoop response. Each snooper is capable of responding at different times (i.e., each snooper operates with different snoop latencies). The bus controller individually tracks the snoop response received from each snooper with the snooperPresent signal enabled. Whenever the snooper wishes to deactivate its snooping capabilities/operations, the snooper de-asserts the snooperPresent signal. The bus controller recognizes this as an indication that the snooper is unavailable. Thus, when the bus controller broadcasts subsequent snoop requests, the bus controller does not send the snoop request to the snooper.
摘要翻译： 具有能够动态地启用和禁用其窥探能力（即，窥探检测和响应）的窥探者的数据处理系统。 窥探者通过多个互连连接到总线控制器，包括窥探信号，窥探响应信号和窥探检测信号。 当snooperPresent信号被断言时，后续的窥探请求被发送到snooper，并且窥探者被轮询以进行侦听响应。 每个窥探者都能够在不同的时间进行响应（即，每个窥探者使用不同的侦听延迟进行操作）。 总线控制器单独跟踪snooperPresent信号启用时从每个窥探者接收的窥探响应。 只要窥探者希望取消其窥探能力/操作，窥探者将断言snooperPresent信号。 总线控制器将此识别为snooper不可用的指示。 因此，当总线控制器广播后续的窥探请求时，总线控制器不向窥探者发送窥探请求。
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46.发明申请Methods and Systems for Checking Run-Time Integrity of Secure Code Cross-Reference to Related Applications 有权用于检查安全代码交叉引用到相关应用程序的运行时完整性的方法和系统公开(公告)号：US20090313695A1
公开(公告)日：2009-12-17
申请号：US12485089
申请日：2009-06-16
IPC分类号： G06F12/14
CPC分类号： G06F12/145 , G06F12/1027 , G06F21/52 , G06F21/54 , G06F21/575 , G06F21/629 , G06F21/71 , G06F21/74 , G06F21/79 , G06F21/81 , G06F2221/2105 , G06F2221/2141
摘要： Methods and systems to guard against attacks designed to replace authenticated, secure code with non-authentic, unsecure code and using existing hardware resources in the CPU's memory management unit (MMU) are disclosed. In certain embodiments, permission entries indicating that pages in memory have been previously authenticated as secure are maintained in a translation lookaside buffer (TLB) and checked upon encountering an instruction residing at an external page. A TLB permission entry indicating permission is invalid causes on-demand authentication of the accessed page. Upon authentication, the permission entry in the TLB is updated to reflect that the page has been authenticated. As another example, in certain embodiments, a page of recently authenticated pages is maintained and checked upon encountering an instruction residing at an external page.
摘要翻译： 公开了用于防止旨在用非真实的，不安全的代码替换已认证的安全代码并且使用CPU的存储器管理单元（MMU）中的现有硬件资源的攻击的方法和系统。 在某些实施例中，指示存储器中的页面已经被先前认证为安全的许可条目保持在翻译后备缓冲器（TLB）中，并且在遇到驻留在外部页面上的指令时进行检查。 指示许可的TLB许可条目是无效的，导致访问页面的按需认证。 认证后，TLB中的许可条目被更新以反映该页面已被认证。 作为另一示例，在某些实施例中，在遇到驻留在外部页面上的指令时，维护和检查最近被认证的页面的页面。
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公开(公告)号：US07152155B2
公开(公告)日：2006-12-19
申请号：US11061981
申请日：2005-02-18
申请人： Michael Scott McIlvaine , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
发明人： Michael Scott McIlvaine , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3861
摘要： When a branch misprediction in a pipelined processor is discovered, if the mispredicted branch instruction is not the last uncommitted instruction in the pipelines, older uncommitted instructions are checked for dependency on a long latency operation. If one is discovered, all uncommitted instructions are flushed from the pipelines without waiting for the dependency to be resolved. The branch prediction is corrected, and the branch instruction and all flushed instructions older than the branch instruction are re-fetched and executed.
摘要翻译： 当发现流水线处理器中的分支错误预测时，如果错误的分支指令不是管道中的最后一条未提交的指令，则会检查较长的未提交的指令对长时间延迟操作的依赖性。 如果被发现，所有未提交的指令都将从管道中刷新，而不必等待解决依赖关系。 纠正分支预测，并且重新获取并执行分支指令和比分支指令更早的所有刷新指令。
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48.发明授权Methods and systems for checking run-time integrity of secure code cross-reference to related applications 有权用于检查安全代码的运行时完整性的方法和系统交叉引用到相关应用程序公开(公告)号：US08639943B2
公开(公告)日：2014-01-28
申请号：US12485089
申请日：2009-06-16
CPC分类号： G06F12/145 , G06F12/1027 , G06F21/52 , G06F21/54 , G06F21/575 , G06F21/629 , G06F21/71 , G06F21/74 , G06F21/79 , G06F21/81 , G06F2221/2105 , G06F2221/2141
摘要： Methods and systems to guard against attacks designed to replace authenticated, secure code with non-authentic, unsecure code and using existing hardware resources in the CPU's memory management unit (MMU) are disclosed. In certain embodiments, permission entries indicating that pages in memory have been previously authenticated as secure are maintained in a translation lookaside buffer (TLB) and checked upon encountering an instruction residing at an external page. A TLB permission entry indicating permission is invalid causes on-demand authentication of the accessed page. Upon authentication, the permission entry in the TLB is updated to reflect that the page has been authenticated. As another example, in certain embodiments, a page of recently authenticated pages is maintained and checked upon encountering an instruction residing at an external page.
摘要翻译： 公开了用于防止旨在用非真实的，不安全的代码替换已认证的安全代码并且使用CPU的存储器管理单元（MMU）中的现有硬件资源的攻击的方法和系统。 在某些实施例中，指示存储器中的页面已经被先前认证为安全的许可条目保持在翻译后备缓冲器（TLB）中，并且在遇到驻留在外部页面上的指令时进行检查。 指示许可的TLB许可条目是无效的，导致访问页面的按需认证。 认证后，TLB中的许可条目被更新以反映该页面已被认证。 作为另一示例，在某些实施例中，在遇到驻留在外部页面上的指令时，维护和检查最近被认证的页面的页面。
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49.发明授权Sending thread message generated using DCR command pointed message control block storing message and response memory address in multiprocessor 失效发送使用DCR命令生成的线程消息指向消息控制块在多处理器中存储消息和响应存储器地址公开(公告)号：US07281118B2
公开(公告)日：2007-10-09
申请号：US11198042
申请日：2005-08-05
IPC分类号： G06F15/167
CPC分类号： G06F13/28
摘要： A method and system for messaging between processors and co-processors connected through a bus. The method permits a multi-thread system processor to request the services of a processor or co-processor located on the bus. Message control blocks are stored in a memory which identify the physical address of the target processor, as well as a memory location in the memory dedicated to the thread requesting the service. When the system processor requests service of a processor or co-processor, a DCR command is created pointing to the message control block. A message is built from information contained in the message control block or transferred to the processor or co-processor. The return address for the processor or co-processor message is concatenated with the thread number, so that the processor or co-processor can create a return message specifically identifying memory space dedicated to the requesting thread for storage of the response message.
摘要翻译： 用于通过总线连接的处理器和协处理器之间的消息传递的方法和系统。 该方法允许多线程系统处理器请求位于总线上的处理器或协处理器的服务。 消息控制块存储在识别目标处理器的物理地址的存储器中，以及专用于请求服务的线程的存储器中的存储器位置。 当系统处理器请求处理器或协处理器的服务时，创建指向消息控制块的DCR命令。 消息由消息控制块中包含的信息构建或传送到处理器或协处理器。 处理器或协处理器消息的返回地址与线程号连接，使得处理器或协处理器可以创建专用于识别请求线程的存储空间的返回消息以存储响应消息。
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公开(公告)号：US07996616B2
公开(公告)日：2011-08-09
申请号：US11669245
申请日：2007-01-31
IPC分类号： G06F12/00
摘要： Techniques and methods are used to control allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby castouts are controlled. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information.
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