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    Sending thread message generated using DCR command pointed message control block storing message and response memory address in multiprocessor
    1.
    发明授权
    Sending thread message generated using DCR command pointed message control block storing message and response memory address in multiprocessor 失效
    发送使用DCR命令生成的线程消息指向消息控制块在多处理器中存储消息和响应存储器地址

    公开(公告)号：US07281118B2

    公开(公告)日：2007-10-09

    申请号：US11198042

    申请日：2005-08-05

    申请人： Jeffrey Todd Bridges ,  Gordon Taylor Davis ,  Thomas Andrew Sartorius ,  Michael Steven Siegel

    发明人： Jeffrey Todd Bridges ,  Gordon Taylor Davis ,  Thomas Andrew Sartorius ,  Michael Steven Siegel

    IPC分类号： G06F15/167

    CPC分类号： G06F13/28

    摘要： A method and system for messaging between processors and co-processors connected through a bus. The method permits a multi-thread system processor to request the services of a processor or co-processor located on the bus. Message control blocks are stored in a memory which identify the physical address of the target processor, as well as a memory location in the memory dedicated to the thread requesting the service. When the system processor requests service of a processor or co-processor, a DCR command is created pointing to the message control block. A message is built from information contained in the message control block or transferred to the processor or co-processor. The return address for the processor or co-processor message is concatenated with the thread number, so that the processor or co-processor can create a return message specifically identifying memory space dedicated to the requesting thread for storage of the response message.

    摘要翻译： 用于通过总线连接的处理器和协处理器之间的消息传递的方法和系统。 该方法允许多线程系统处理器请求位于总线上的处理器或协处理器的服务。 消息控制块存储在识别目标处理器的物理地址的存储器中，以及专用于请求服务的线程的存储器中的存储器位置。 当系统处理器请求处理器或协处理器的服务时，创建指向消息控制块的DCR命令。 消息由消息控制块中包含的信息构建或传送到处理器或协处理器。 处理器或协处理器消息的返回地址与线程号连接，使得处理器或协处理器可以创建专用于识别请求线程的存储空间的返回消息以存储响应消息。

    Latency Insensitive FIFO Signaling Protocol
    4.
    发明申请
    Latency Insensitive FIFO Signaling Protocol 有权
    延迟不敏感的FIFO信令协议

    公开(公告)号：US20080281996A1

    公开(公告)日：2008-11-13

    申请号：US12179970

    申请日：2008-07-25

    申请人： Kenneth Alan Dockser ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Robert Douglas Clancy ,  Thomas Andrew Sartorius

    发明人： Kenneth Alan Dockser ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Robert Douglas Clancy ,  Thomas Andrew Sartorius

    IPC分类号： G06F13/38 ,  G06F3/00

    CPC分类号： G06F13/4059 ,  G06F5/06 ,  G06F2205/126

    摘要： Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.

    摘要翻译： 来自以第一数据速率运行的源域的数据被传送到以不同数据速率工作的另一个域中的FIFO。 FIFO在传输到宿之前缓冲数据以进一步处理或存储。 源端计数器跟踪FIFO中可用的空间。 在公开的示例中，初始计数器值对应于FIFO深度。 响应于来自源域的数据就绪信号，计数器无延迟地递减。 响应于来自接收器域的信令从FIFO读取数据，计数器递增。 因此，增量受到域之间的信令等待时间的限制。 当计数器指示FIFO已满时，源可能再发送一次数据。 数据的最后一次节拍从源头连续发送到指示FIFO位置可用为止; 有效提供一个FIFO位置。

    Methods and apparatus to insure correct predecode
    5.
    发明授权
    Methods and apparatus to insure correct predecode 有权
    确保正确预解码的方法和装置

    公开(公告)号：US07376815B2

    公开(公告)日：2008-05-20

    申请号：US11066957

    申请日：2005-02-25

    申请人： Rodney Wayne Smith ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

    发明人： Rodney Wayne Smith ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30149 ,  G06F8/447 ,  G06F9/382

    摘要： Techniques for ensuring a synchronized predecoding of an instruction string are disclosed. The instruction string contains instructions from a variable length instruction set and embedded data. One technique includes defining a granule to be equal to the smallest length instruction in the instruction set and defining the number of granules that compose the longest length instruction in the instruction set to be MAX. The technique further includes determining the end of an embedded data segment, when a program is compiled or assembled into the instruction string and inserting a padding of length, MAX−1, into the instruction string to the end of the embedded data. Upon predecoding of the padded instruction string, a predecoder maintains synchronization with the instructions in the padded instruction string even if embedded data is coincidentally encoded to resemble an existing instruction in the variable length instruction set.

    摘要翻译： 公开了用于确保指令串的同步预解码的技术。 指令串包含来自可变长度指令集和嵌入数据的指令。 一种技术包括定义一个等于指令集中最小长度指令的粒子，并将构成指令集中最长指令的粒子数定义为MAX。 该技术还包括当程序被编译或组装成指令串并将长度为MAX-1的填充插入到嵌入数据的结尾的指令串中时，确定嵌入数据段的结束。 在预编译填充指令串时，即使嵌入数据被巧合地编码成类似于可变长度指令集中的现有指令，预解码器也保持与填充指令串中的指令的同步。

    Speculative instruction issue in a simultaneously multithreaded processor
    6.
    发明授权
    Speculative instruction issue in a simultaneously multithreaded processor 失效
    同时多线程处理器中的推测性指令问题

    公开(公告)号：US07366877B2

    公开(公告)日：2008-04-29

    申请号：US10664384

    申请日：2003-09-17

    申请人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

    发明人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3836 ,  G06F9/3826 ,  G06F9/3851

    摘要： A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic speculatively issues instructions from a given thread based on the probability that the required operands will be available when the instruction reaches the stage in the pipeline where they are required. Issue of an instruction is blocked if the current pipeline conditions indicate that there is a significant probability that the instruction will need to stall in a shared resource to wait for operands. Once the probability that the instruction will stall is below a certain threshold, based on current pipeline conditions, the instruction is allowed to issue.

    摘要翻译： 一种用于优化微处理器中能够同时处理多个指令线程的吞吐量的方法。 在输入缓冲器和微处理器的流水线之间提供指令发生逻辑。 指令问题逻辑根据当指令到达需要的流水线中的阶段时，基于所需操作数将可用的概率来推测来自给定线程的指令。 如果当前流水线条件表明指令需要在共享资源中停止以等待操作数的重要概率，则指令的发出被阻止。 一旦指令停顿的概率低于某个阈值，则根据当前流水线条件，允许发出指令。

    Methods, cache memories, systems and computer program products for storing transient, normal, and locked entries in an associative cache memory
    7.
    发明授权
    Methods, cache memories, systems and computer program products for storing transient, normal, and locked entries in an associative cache memory 失效
    方法，缓存存储器，系统和计算机程序产品，用于在关联高速缓冲存储器中存储瞬态，正常和锁定条目

    公开(公告)号：US06560677B1

    公开(公告)日：2003-05-06

    申请号：US09304664

    申请日：1999-05-04

    申请人： Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

    发明人： Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

    IPC分类号： G06F1208

    CPC分类号： G06F9/30043 ,  G06F12/0864 ,  G06F12/121 ,  G06F12/126 ,  G06F12/128

    摘要： Ways of a cache memory system are designated as being in one of three subsets: a normal subset, a transient subset, and a locked subset. The designation of the respective subsets is provided by a normal subset floor index, a transient subset floor index, and a transient subset ceiling index. The respective indexes are used to select the subset into which new entries are copied from main memory as a result of a cache miss. If the new entry is designated as being characterized by normal program behavior, it is copied into the normal subset in the cache. If the new entry is designated as being characterized by transient program behavior, it is copied into the transient subset in the cache. The relationship between the normal subset and the transient subset is programmable. For example, the normal and the transient subsets may include at least one common way of the cache memory or the transient subset may be completely included in the normal subset or completely separate therefrom.

    摘要翻译： 缓存存储器系统的方式被指定为三个子集之一：正常子集，瞬变子集和锁定子集。 相应子集的指定由正常子集层索引，瞬时子集底层索引和瞬时子集上限索引提供。 相应的索引用于选择由于高速缓存未命中而从主存储器复制新条目的子集。 如果新条目被指定为通过正常程序行为表征，则将其复制到缓存中的正常子集中。 如果新条目被指定为由瞬时程序行为表征，则将其复制到缓存中的瞬态子集中。 正常子集与瞬态子集之间的关系是可编程的。 例如，正常和瞬态子集可以包括高速缓冲存储器的至少一种常见方式，或者瞬态子集可以完全包含在正常子集中或与其完全分开。

    Address pipelining for data transfers
    8.
    发明授权
    Address pipelining for data transfers 失效
    地址流水线进行数据传输

    公开(公告)号：US6081860A

    公开(公告)日：2000-06-27

    申请号：US975545

    申请日：1997-11-20

    申请人： Jeffrey Todd Bridges ,  Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer

    发明人： Jeffrey Todd Bridges ,  Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer

    IPC分类号： G06F13/364 ,  G06F13/00

    CPC分类号： G06F13/364

    摘要： A process and system for transferring data including at least one slave device connected to at least one master device through an arbiter device. The master and slave devices are connected by a single address bus, a write data bus and a read data bus. The arbiter device receives requests for data transfers from the master devices and selectively transmits the requests to the slave devices. The master devices and the slave devices are further connected by a plurality of transfer qualifier signals which may specify predetermined characteristics of the requested data transfers. Control signals are also communicated between the arbiter device and the slave devices to allow appropriate slave devices to latch addresses of requested second transfers during the pendency of current or primary data transfers so as to obviate an address transfer latency typically required for the second transfer. The design is configured to advantageously function in mixed systems which may include address-pipelining and non-address-pipelining slave devices.

    摘要翻译： 一种用于传送数据的过程和系统，包括通过仲裁设备连接到至少一个主设备的至少一个从设备。 主设备和从设备通过单个地址总线，写数据总线和读数据总线连接。 仲裁设备接收来自主设备的数据传输请求，并选择性地将请求发送到从设备。 主设备和从设备通过可以指定所请求的数据传输的预定特性的多个传输限定符信号进一步连接。 控制信号也在仲裁设备和从设备之间通信，以允许适当的从设备在当前或主要数据传输的未决期间锁存所请求的第二传送的地址，以便消除通常为第二传送所需的地址传输等待时间。 该设计被配置为有利地在可以包括地址流水线和非地址流水线从设备的混合系统中起作用。

    System and method for tracing program execution within a processor before and after a triggering event
    9.
    发明授权
    System and method for tracing program execution within a processor before and after a triggering event 失效
    在触发事件之前和之后跟踪处理器内的程序执行的系统和方法

    公开(公告)号：US5996092A

    公开(公告)日：1999-11-30

    申请号：US760553

    申请日：1996-12-05

    申请人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Thomas K. Collopy ,  James N. Dieffenderfer ,  Thomas Andrew Sartorius

    发明人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Thomas K. Collopy ,  James N. Dieffenderfer ,  Thomas Andrew Sartorius

    IPC分类号： G06F11/34 ,  G06F11/30

    CPC分类号： G06F11/3466

    摘要： A system and method for tracing program code within a processor having an embedded cache memory. The non-invasive tracing technique minimizes the need for trace information to be broadcast externally. The tracing technique monitors changes in instruction flow from the normal execution stream of the code. The tracing technique monitors the updating of processor branch target register contents in order to monitor branch target flow of the code. Tracing of the program flow includes tracing instructions both before and after a trace triggering event. The implementation of periodic synchronizing events enables the tracing of instructions occurring before and after a triggering event.

    摘要翻译： 一种用于在具有嵌入式高速缓冲存储器的处理器内跟踪程序代码的系统和方法。 非侵入性跟踪技术最大限度地减少了要在外部广播的跟踪信息的需要。 跟踪技术监视来自代码的正常执行流的指令流程的变化。 跟踪技术监控处理器分支目标寄存器内容的更新，以便监视代码的分支目标流。 跟踪程序流程包括跟踪触发事件之前和之后的跟踪指令。 周期性同步事件的实现使得能够跟踪在触发事件之前和之后发生的指令。