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公开(公告)号：US20080094896A1
公开(公告)日：2008-04-24
申请号：US11550918
申请日：2006-10-19
申请人： Karl R. Erickson , John A. Fifield , Chandrasekara Kothandaraman , Phil C. Paone , William R. Tonti
发明人： Karl R. Erickson , John A. Fifield , Chandrasekara Kothandaraman , Phil C. Paone , William R. Tonti
摘要： The embodiments of the invention provide an apparatus, method, etc. for a non volatile memory RAD-hard (NVM-rh) system. More specifically, an IC permanent non-volatile storage element comprises an integrated semiconductor stable reference component, wherein the component is resistant to external radiation. The storage element further comprises e-fuse structures in the component and a sensing circuit coupled to the e-fuse structures. The sensing circuit is adapted to update an external device at a specified time interval to reduce incidence of soft errors and errors due to power failure. Moreover, the sensing circuit is adapted to cease updating the external device to program the e-fuse structures; and, continue updating the external device after programming the e-fuse structures.
摘要翻译： 本发明的实施例提供了一种用于非易失性存储器RAD-hard（NVM-rh）系统的装置，方法等。 更具体地，IC永久性非易失性存储元件包括集成半导体稳定参考元件，其中该元件对外部辐射具有耐受性。 存储元件还包括组件中的e熔丝结构和耦合到电熔丝结构的感测电路。 感测电路适于以特定的时间间隔更新外部设备，以减少由于电源故障引起的软错误和错误的发生。 此外，感测电路适于停止更新外部设备以编程电熔丝结构; 并且在编程电熔丝结构之后继续更新外部设备。
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公开(公告)号：US07268577B2
公开(公告)日：2007-09-11
申请号：US11016220
申请日：2004-12-17
申请人： Karl R. Erickson , John A. Fifield , Chandrasekharan Kothandaraman , Phil C. Paone , William R. Tonti
发明人： Karl R. Erickson , John A. Fifield , Chandrasekharan Kothandaraman , Phil C. Paone , William R. Tonti
IPC分类号： H03K19/00
CPC分类号： G06F21/71
摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fuses (eFUSES).
摘要翻译： 提供了在设备已经离开制造商的控制之后可以控制电子设备的特定特征的操作和/或访问的技术和系统。 操作和/或访问可以基于存储在诸如电可编程熔丝（eFUSES）的非易失性存储元件中的值来提供。
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43.发明授权公开(公告)号：US06879638B1
公开(公告)日：2005-04-12
申请号：US09473935
申请日：1999-12-28
CPC分类号： H04L25/4906 , H04L25/4902
摘要： A method and system for providing communication between electronic devices that uses the phase of data transmitted between the devices to indicate logical one and zero values. The method and system has the added benefit of relieving the traditional limitations of voltage communication restraints between devices having differing core voltages (i.e. Differing generations).
摘要翻译： 一种用于在电子设备之间提供通信的方法和系统，其使用在设备之间传输的数据的相位来指示逻辑1和零值。 该方法和系统具有减轻在具有不同核心电压的器件（即不同代）之间的电压通信约束的传统限制的附加益处。
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公开(公告)号：US06496037B1
公开(公告)日：2002-12-17
申请号：US09588202
申请日：2000-06-06
IPC分类号： H03K190175
CPC分类号： H03K19/0005
摘要： An automatic driver adjuster and methods using the same are provided that modify off-chip drivers based on load characteristics. The preferred embodiments are preferably automatic and require little or no human intervention. Preferred embodiments of the current invention analyze and determine the impedance of a node and adjust a number of output drivers in response to the impedance of the node, or analyze a resultant waveform of the node, caused by an input waveform, and adjust a number of output drivers in response to the resultant waveform of the node.
摘要翻译： 提供了一种自动驱动器调节器及其使用方法，其基于负载特性修改片外驱动器。 优选的实施方案优选是自动的，并且需要很少的或不需要人为干预。 本发明的优选实施例分析和确定节点的阻抗并且响应于节点的阻抗调整输出驱动器的数量，或者分析由输入波形引起的节点的合成波形，并且调整多个 输出驱动器响应于该结点的合成波形。
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公开(公告)号：US06268748B1
公开(公告)日：2001-07-31
申请号：US09073517
申请日：1998-05-06
申请人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Christopher P. Miller , William R. Tonti
发明人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Christopher P. Miller , William R. Tonti
IPC分类号： G03K19094
CPC分类号： G11C7/1069 , G11C7/1051 , H03K19/0016 , H03K19/09429
摘要： An electronic semiconductor module, either memory or logic, having a driver circuit which includes a multiplicity of driver transistors, together with circuitry for simultaneously applying a first positive bias to a first select number of driver transistors to activate them to an operational state, a second positive bias to a second select number of driver transistors to place them in readiness for activation, and a negative bias to the remaining driver transistors to place them in a fully inactive state thereby reducing noise in the driver circuit. The first positive bias is greater than the transistor threshold voltage, preferably greater than two volts, the second positive bias is less than the threshold voltage, preferably less than one volt, and the negative bias is in the order of minus 0.3 volt. A method of reducing noise in the electronic semiconductor module is also described and includes the applying of a positive bias to a first select number of the transistors to activate them while simultaneously applying a second positive bias to a second select number of the transistors to ready them for activation, and a negative voltage to the remaining transistors to place each in a inactive condition.
摘要翻译： 一种电子半导体模块，无论是存储器还是逻辑，具有包括多个驱动器晶体管的驱动器电路，以及用于同时向第一选择数量的驱动器晶体管施加第一正偏置以将其激活到操作状态的电路，第二 对第二选择数量的驱动器晶体管施加正偏置以使它们准备激活，以及对其余驱动器晶体管的负偏置以将它们置于完全无效状态，从而降低驱动器电路中的噪声。 第一正偏压大于晶体管阈值电压，优选大于2伏，第二正偏压小于阈值电压，优选小于1伏特，负偏压为零下0.3伏。 还描述了降低电子半导体模块中的噪声的方法，并且包括将正偏压施加到第一选择数量的晶体管以激活它们，同时向第二选择数量的晶体管施加第二正偏置以准备它们 用于激活，并且向剩余晶体管施加负电压以使其处于非活动状态。
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公开(公告)号：US5757693A
公开(公告)日：1998-05-26
申请号：US803056
申请日：1997-02-19
申请人： Russell J. Houghton , Claude L. Bertin , John A. Fifield , Christopher P. Miller , William R. Tonti
发明人： Russell J. Houghton , Claude L. Bertin , John A. Fifield , Christopher P. Miller , William R. Tonti
IPC分类号： G11C11/402 , G11C11/403 , G11C11/405 , G11C11/24
CPC分类号： G11C11/405 , G11C11/403
摘要： A gain cell in a memory array having read and write bitlines and wordlines, wherein the gain cell comprises a write transistor, a storage node, a read transistor, and a diode is disclosed. The write transistor allows the value of the write bitline to be stored onto the storage node when activated by the write wordline. The read transistor, which allows the stored value to be read, is coupled to the storage node and to the read bitline via the diode. The diode prevents the conduction of the read transistor in the opposite direction, thus preventing read interference from other cells and reducing bitline capacitance.
摘要翻译： 具有读和写位线和字线的存储器阵列中的增益单元，其中增益单元包括写晶体管，存储节点，读晶体管和二极管。 当由写入字线激活时，写入晶体管允许将写入位线的值存储到存储节点上。 允许读取存储值的读取晶体管通过二极管耦合到存储节点和读取位线。 二极管防止读取晶体管在相反方向的导通，从而防止来自其他单元的读取干扰并减少位线电容。
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公开(公告)号：US08184465B2
公开(公告)日：2012-05-22
申请号：US12911379
申请日：2010-10-25
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.
摘要翻译： 可编程器件包括衬底（10）; 绝缘体（13）; 绝缘体上的细长半导体材料（12），具有第一和第二端的细长半导体材料和上表面S; 第一端部（12a）比第二端部（12b）大得多，金属材料设置在上表面上; 所述金属材料可响应于流过半导体材料和金属材料的电流I而沿着上表面物理迁移。
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公开(公告)号：US07981731B2
公开(公告)日：2011-07-19
申请号：US11482688
申请日：2006-07-07
IPC分类号： H01L21/82
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , Y10S438/957 , H01L2924/00
摘要： A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a second insulator disposed between the substrate and said electrode of said second device, said second insulator having a second value of said given characteristic that is different from said first value. The electrodes of the diode and the FET are coupled to one another, and a source of programming energy is coupled to the diode to cause it to permanently decrease in resistivity when programmed. The programmed state of the diode is indicated by a current in the FET, which is read by a sense latch. Thus a small resistance change in the diode translates to a large signal gain/change in the latch. This allows the diode to be programmed at lower voltages.
摘要翻译： 一种可编程元件，其具有第一二极管，其具有电极和布置在所述基板和所述第一器件的所述电极之间的第一绝缘体，所述第一绝缘体具有给定特性的第一值，以及具有电极和设置在所述第二绝缘体中的第二绝缘体的FET 在所述基板和所述第二装置的所述电极之间，所述第二绝缘体具有与所述第一值不同的所述给定特性的第二值。 二极管和FET的电极彼此耦合，并且编程能量源耦合到二极管，以使其在编程时永久地降低电阻率。 二极管的编程状态由FET中的电流表示，该电流由读出锁存器读取。 因此，二极管中的小电阻变化转换为锁存器中的大信号增益/变化。 这允许二极管在较低的电压下被编程。
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公开(公告)号：US07872897B2
公开(公告)日：2011-01-18
申请号：US10552971
申请日：2003-04-30
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.
摘要翻译： 可编程器件包括衬底（10）; 绝缘体（13）; 绝缘体上的细长半导体材料（12），具有第一和第二端的细长半导体材料和上表面S; 第一端部（12a）比第二端部（12b）大得多，金属材料设置在上表面上; 所述金属材料可响应于流过半导体材料和金属材料的电流I而沿着上表面物理迁移。
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公开(公告)号：US07551470B2
公开(公告)日：2009-06-23
申请号：US11550918
申请日：2006-10-19
申请人： Karl R. Erickson , John A. Fifield , Chandrasekara Kothandaraman , Phil C. Paone , William R. Tonti
发明人： Karl R. Erickson , John A. Fifield , Chandrasekara Kothandaraman , Phil C. Paone , William R. Tonti
IPC分类号： G11C17/00
摘要： The embodiments of the invention provide an apparatus, method, etc. for a non volatile memory RAD-hard (NVM-rh) system. More specifically, an IC permanent non-volatile storage element comprises an integrated semiconductor stable reference component, wherein the component is resistant to external radiation. The storage element further comprises e-fuse structures in the component and a sensing circuit coupled to the e-fuse structures. The sensing circuit is adapted to update an external device at a specified time interval to reduce incidence of soft errors and errors due to power failure. Moreover, the sensing circuit is adapted to cease updating the external device to program the e-fuse structures; and, continue updating the external device after programming the e-fuse structures.
摘要翻译： 本发明的实施例提供了一种用于非易失性存储器RAD-hard（NVM-rh）系统的装置，方法等。 更具体地，IC永久性非易失性存储元件包括集成半导体稳定参考元件，其中该元件对外部辐射具有耐受性。 存储元件还包括组件中的e熔丝结构和耦合到电熔丝结构的感测电路。 感测电路适于以特定的时间间隔更新外部设备，以减少由于电源故障引起的软错误和错误的发生。 此外，感测电路适于停止更新外部设备以编程电熔丝结构; 并且在编程电熔丝结构之后继续更新外部设备。
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