公开(公告)号：US06359468B1

公开(公告)日：2002-03-19

申请号：US09516865

申请日：2000-03-02

Applicant: James Park ,  Wei-Jen Huang ,  Tony Ngai ,  Bruce B. Pedersen

Inventor： James Park ,  Wei-Jen Huang ,  Tony Ngai ,  Bruce B. Pedersen

IPC: H03K19177

CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17792

Abstract: A programmable logic device is adapted to predict carry values in long-chain-carry logic configurations. In the most preferred embodiment, which functions in any long-carry-chain logic configuration, each logic region calculates a result for both values of the carry-in signal to that region, and when a carry signal for the group to which the region belongs reaches the region, the correct result in each region, and thence the correct carry-out for that group, are calculated and propagated. The carry-out terminal of one group is arranged to be adjacent to the carry-in terminal of the next group, to enhance carry propagation speed. In another embodiment, each region looks back two regions to predict the carry-in. In two additional embodiments, logic is provided to mathematically calculate the carry values.

Abstract translation: 可编程逻辑器件适用于预测长链进位逻辑配置中的进位值。 在最优选的实施例中，其在任何长承载链逻辑配置中起作用，每个逻辑区域计算对于该区域的进位信号的两个值的结果，以及当该区域所属的组的进位信号 到达该地区，每个地区的正确结果，然后计算和传播该组的正确进行。 一组的进位终端被布置成与下一组的进位终端相邻，以提高进位传播速度。 在另一个实施例中，每个区域回顾两个区域以预测携带。 在两个附加实施例中，提供逻辑以在数学上计算进位值。

公开(公告)号：US06351144B1

公开(公告)日：2002-02-26

申请号：US09615926

申请日：2000-07-13

Applicant: Sergey Shumarayev ,  Wei-Jen Huang ,  Rakesh Patel

Inventor： Sergey Shumarayev ,  Wei-Jen Huang ,  Rakesh Patel

IPC: G06F738

CPC classification number: H01L23/5382 ,  H01L27/118 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A programmable logic device including a set of aligned unified cells, with each unified cell including one or more logic array blocks and a set of signal interface bumps. An input/output band of each unified cell is aligned with input/output bands of adjacent unified cells. A trace is positioned between each signal interface bump and the input/output band. The input/output band of each unified cell is responsible for providing an input/output interface for the logic array block(s) of that unified cell. Signal interface bumps of a unified cell may be coupled to those of another cell via the package. As a result, row and column interconnect circuitry present in conventional programmable logic devices can be obviated. In another aspect of the invention, a grid of signal interface bumps is formed on a die. A package with a solder ball is positioned within the grid of signal interface bumps. A set of package routing leads is positioned between the grid of signal interface bumps and the solder ball.

Abstract translation: 包括一组对准的统一单元的可编程逻辑器件，每个统一单元包括一个或多个逻辑阵列块和一组信号接口凸块。 每个统一单元的输入/输出带与相邻统一单元的输入/输出带对齐。 轨迹位于每个信号界面凸块和输入/输出带之间。 每个统一单元的输入/输出频带负责提供该统一单元的逻辑阵列块的输入/输出接口。 统一单元的信号接口凸起可以经由封装耦合到另一个单元的信号接口凸块。 结果，可以避免存在于常规可编程逻辑器件中的行和列互连电路。 在本发明的另一方面，在模具上形成栅格的信号界面凸块。 具有焊球的封装位于信号接口凸块的栅格内。 一组封装路由引线位于信号接口凸块和焊球之间。

公开(公告)号：US06323680B1

公开(公告)日：2001-11-27

申请号：US09517350

申请日：2000-03-02

Applicant: Bruce B. Pedersen ,  Sergey Shumarayev ,  Wei-Jen Huang ,  Vinson Chan ,  Stephen Brown ,  Tony Ngai ,  James Park

Inventor： Bruce B. Pedersen ,  Sergey Shumarayev ,  Wei-Jen Huang ,  Vinson Chan ,  Stephen Brown ,  Tony Ngai ,  James Park

IPC: G06F738

CPC classification number: H03K19/17736 ,  G06F7/5443 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17732

Abstract: A programmable logic device is configured to accommodate multiplication by the provision in each logic region of specialized components to form and sum partial products. The specialized components are separate from the ordinary logic of the logic region, and their presence imposes little penalty on the performance of ordinary logic functions, while enhancing the speed at which multiplication is performed by minimizing the number of logic regions used for a particular multiplication operation, and also minimizing the use of the interconnection resources of the device to convey signals among those regions.

Abstract translation: 可编程逻辑器件被配置为通过专用部件的每个逻辑区域中的提供来适应乘法，以形成和求和部分乘积。 专门的部件与逻辑区域的普通逻辑分开，并且它们的存在对普通逻辑功能的性能施加了很小的损失，同时通过最小化用于特定乘法运算的逻辑区域的数量来提高执行乘法的速度 并且还最小化设备的互连资源在这些区域之间传送信号的使用。