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    Embedded memory blocks for programmable logic
    1.
    发明授权
    Embedded memory blocks for programmable logic 有权

    公开(公告)号：US06593772B2

    公开(公告)日：2003-07-15

    申请号：US10177785

    申请日：2002-06-19

    申请人： Tony Ngai ,  Sergey Shumarayev ,  Wei-Jen Huang ,  Rakesh Patel ,  Tin Lai

    发明人： Tony Ngai ,  Sergey Shumarayev ,  Wei-Jen Huang ,  Rakesh Patel ,  Tin Lai

    IPC分类号： H03K19177

    CPC分类号： G11C5/025 ,  H03K19/17736 ,  H03K19/1776

    摘要： A high-performance programmable logic architecture has embedded memory (608). arranged at the peripheries or edges of the integrated circuit. This enhances the performance of the programmable logic integrated circuit by shortening the lengths of the programmable interconnect (748). In a specific embodiment, the memory blocks (703) are organized in rows along the top and bottom edges of the integrated circuit. The logic elements (805) can be directly programmable routed and connected to driver blocks (809) of the logic block in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources (815, 825). Using similar direct programmable interconnections (828, 830, 835), the logic blocks can directly programmable connect to the memory blocks without using the global programmable interconnect resources. The present invention also provides technique of flexibly combining or stitching multiple memories together to form memories of a desired size.

    Memory circuitry for programmable logic integrated circuit devices
    2.
    发明授权
    Memory circuitry for programmable logic integrated circuit devices 有权

    公开(公告)号：US06556502B2

    公开(公告)日：2003-04-29

    申请号：US10134886

    申请日：2002-04-26

    申请人： Tony Ngai ,  Nitin Prasad ,  Thungoc Tran

    发明人： Tony Ngai ,  Nitin Prasad ,  Thungoc Tran

    IPC分类号： G11C800

    CPC分类号： H03K19/1776 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/005

    摘要： A programmable logic device includes, in addition to the usual regions of programmable logic and the programmable interconnect, at least one region of memory which has multiple independently usable write and/or read ports (e.g., two write ports and two read ports). Every memory cell in the memory region is accessible from any of these ports. This enables the memory region to be used to provide either one relatively large memory or two somewhat smaller memories, each occupying a fraction of the full memory. In the latter case, the two memories provided can have any of many different sizes relative to one another. Many different modes or combinations of modes of operating the memory region or parts of the memory region are possible.

    Interconnection resources for programmable logic integrated circuit devices
    10.
    发明授权
    Interconnection resources for programmable logic integrated circuit devices 失效
    可编程逻辑集成电路器件的互连资源

    公开(公告)号：US06727727B2

    公开(公告)日：2004-04-27

    申请号：US10299572

    申请日：2002-11-18

    申请人： James Schleicher ,  James Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

    发明人： James Schleicher ,  James Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

    IPC分类号： H03K190177

    CPC分类号： G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17792

    摘要： A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

    摘要翻译： 可编程逻辑器件具有许多可编程逻辑区域，以及可用于在几乎任何逻辑区域之间进行互连的相对通用的，可编程的互连资源。 此外，各种类型的更多本地互连资源与每个逻辑区域相关联，以便于在相邻或附近的逻辑区域之间建立互连，而不需要使用这些互连的通用互连资源。 本地互连资源通过相对直接的和因此的高速互连来支持逻辑区域的灵活聚集，优选地在逻辑区域的典型二维阵列中的水平和垂直方向。 由本地互连资源提供的逻辑区域聚类选项优选地在逻辑区域阵列内是无边界的或基本无边界的。