公开(公告)号：US09904476B2

公开(公告)日：2018-02-27

申请号：US12870596

申请日：2010-08-27

Applicant: Wei-Jen Huang ,  Chih-Tsung Huang ,  Sachin Agarwal ,  Sha Ma

Inventor： Wei-Jen Huang ,  Chih-Tsung Huang ,  Sachin Agarwal ,  Sha Ma

IPC: G06F13/16 ,  G06F12/06 ,  G06F3/06 ,  G06F12/0864 ,  G06F11/10 ,  H04L12/773 ,  H04L12/741

CPC classification number: G06F3/0613 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0674 ,  G06F3/0679 ,  G06F11/108 ,  G06F12/06 ,  G06F12/0864 ,  G06F13/1642 ,  G06F13/1673 ,  H04L45/60 ,  H04L45/745

Abstract: Techniques are described for a memory device. In various embodiments, a scheduler/controller is configured to manage data as it read to or written from a memory. A memory is partitioned into a group of sub-blocks, a parity block is associated with the sub-blocks, and the sub-blocks are accessed to read data as needed. A pending write buffer is added to a group of memory sub-blocks. Such a buffer may be sized to be equal to the group of memory sub-blocks. The pending write buffer handles collisions for write accesses to the same block.

公开(公告)号：US20130153178A1

公开(公告)日：2013-06-20

申请号：US13459095

申请日：2012-04-28

Applicant: Shih-Yao LI ,  Jui-Wen HUNG ,  Ching-Bai HWANG ,  Wei-Jen HUANG

Inventor： Shih-Yao LI ,  Jui-Wen HUNG ,  Ching-Bai HWANG ,  Wei-Jen HUANG

IPC: F28D15/00

CPC classification number: H01L23/467 ,  H01L23/4093 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A heat dissipation device includes a bracket, a fan with an air inlet and an air outlet, and a heat sink mounted on the bracket. The bracket includes a plurality of rivets and clasps. Each of the clasps includes a mounting portion, an arm extending upwards from the mounting portion, and a hook portion extending from a top end of the arm and towards the mounting portion. The mounting portion is riveted on the bracket by a corresponding rivet. The fan includes a plurality of ears corresponding to the clasps. The hook portions of the clasps abut on top surfaces of the ears to fix the fan on the bracket. The fan defines a plurality of channels communicating the outlet of the fan.

Abstract translation: 散热装置包括支架，具有空气入口的风扇和空气出口以及安装在支架上的散热器。 支架包括多个铆钉和扣子。 每个扣环包括安装部分，从安装部分向上延伸的臂和从臂的顶端延伸并朝向安装部分的钩部。 安装部分通过相应的铆钉铆接在支架上。 风扇包括对应于扣子的多个耳朵。 钩子的钩部分靠在耳朵的顶表面上，以将风扇固定在支架上。 风扇限定了连通风扇出口的多个通道。

公开(公告)号：US07492188B2

公开(公告)日：2009-02-17

申请号：US11888317

申请日：2007-07-30

Applicant: Tony Ngai ,  Bruce Pedersen ,  Sergey Shumarayev ,  James Schleicher ,  Wei-Jen Huang ,  Michael Hutton ,  Victor Maruri ,  Rakesh Patel ,  Peter J. Kazarian ,  Andrew Leaver ,  David W. Mendel ,  Jim Park

Inventor： Tony Ngai ,  Bruce Pedersen ,  Sergey Shumarayev ,  James Schleicher ,  Wei-Jen Huang ,  Michael Hutton ,  Victor Maruri ,  Rakesh Patel ,  Peter J. Kazarian ,  Andrew Leaver ,  David W. Mendel ,  Jim Park

IPC: H01L25/00 ,  H03K19/177

CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17792

Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

公开(公告)号：US07317332B2

公开(公告)日：2008-01-08

申请号：US11269867

申请日：2005-11-07

Applicant: Tony Ngai ,  Bruce Pedersen ,  Sergey Shumarayev ,  James Schleicher ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

Inventor： Tony Ngai ,  Bruce Pedersen ,  Sergey Shumarayev ,  James Schleicher ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

IPC: H01L25/00 ,  H03K19/177

CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17792

Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

公开(公告)号：US20070080710A1

公开(公告)日：2007-04-12

申请号：US11514692

申请日：2006-09-01

Applicant: James Schleicher ,  Jim Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

Inventor： James Schleicher ,  Jim Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

IPC: H03K19/177

CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17792

Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

公开(公告)号：US07123052B2

公开(公告)日：2006-10-17

申请号：US11087377

申请日：2005-03-22

Applicant: James Schleicher ,  Jim Park ,  Sergey Shumarayev ,  Bruce Pederson ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

Inventor： James Schleicher ,  Jim Park ,  Sergey Shumarayev ,  Bruce Pederson ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

IPC: H03K19/177

CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17792

Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

公开(公告)号：US06727727B2

公开(公告)日：2004-04-27

申请号：US10299572

申请日：2002-11-18

Applicant: James Schleicher ,  James Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

Inventor： James Schleicher ,  James Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

IPC: H03K190177

CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17792

Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

Abstract translation: 可编程逻辑器件具有许多可编程逻辑区域，以及可用于在几乎任何逻辑区域之间进行互连的相对通用的，可编程的互连资源。 此外，各种类型的更多本地互连资源与每个逻辑区域相关联，以便于在相邻或附近的逻辑区域之间建立互连，而不需要使用这些互连的通用互连资源。 本地互连资源通过相对直接的和因此的高速互连来支持逻辑区域的灵活聚集，优选地在逻辑区域的典型二维阵列中的水平和垂直方向。 由本地互连资源提供的逻辑区域聚类选项优选地在逻辑区域阵列内是无边界的或基本无边界的。

公开(公告)号：US06480027B1

公开(公告)日：2002-11-12

申请号：US09516866

申请日：2000-03-02

Applicant: Tony Ngai ,  Sergey Shumarayev ,  Wei-Jen Huang

Inventor： Tony Ngai ,  Sergey Shumarayev ,  Wei-Jen Huang

IPC: H03K19177

CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1778

Abstract: Driver circuitry for programmable logic devices may include a module comprising a driver and associated hardware-programmable input and/or output routing connection. Instances of the generalized driver module may be included anywhere on the programmable logic device that driver circuitry having characteristics within the capabilities of the generalized module is needed. The circuitry of each instance of the module is hardware-customized to match the driver characteristics required for that instance. Driver circuits may be distributed throughout the interconnection conductor resources of the programmable logic device in such a way as to optimize re-buffering of signals propagating through those resources.

Abstract translation: 用于可编程逻辑器件的驱动器电路可以包括包括驱动器和相关联的硬件可编程输入和/或输出路由连接的模块。 广义驱动器模块的实例可以包括在可编程逻辑器件的任何地方，其中需要具有广义模块能力的特性的驱动器电路。 模块的每个实例的电路都是硬件自定义的，以匹配该实例所需的驱动程序特性。 驱动器电路可以分布在可编程逻辑器件的整个互连导体资源中，以便优化通过这些资源传播的信号的重新缓冲。

公开(公告)号：US06469548B1

公开(公告)日：2002-10-22

申请号：US09881354

申请日：2001-06-14

Applicant: Wei-Jen Huang ,  Kuang-Yu Chen

Inventor： Wei-Jen Huang ,  Kuang-Yu Chen

IPC: H03B100

CPC classification number: H03F1/308

Abstract: A circuit comprising a current source, a first amplifier, and a second amplifier. The circuit may be used to provide for crossing point compensation of a CMOS driver as a function of a supply voltage. The current source may be configured to present a reference current. The first amplifier may be configured to (i) receive the reference current as a load, (ii) receive a first voltage, and (iii) present a second voltage responsive to the first voltage. The second amplifier may be configured to (i) receive the second voltage and (ii) change a current at a node responsive to the second voltage.

Abstract translation: 一种包括电流源，第一放大器和第二放大器的电路。 该电路可用于提供作为电源电压的函数的CMOS驱动器的交叉点补偿。 电流源可以被配置为呈现参考电流。 第一放大器可以被配置为（i）作为负载接收参考电流，（ii）接收第一电压，以及（iii）响应于第一电压呈现第二电压。 第二放大器可以被配置为（i）接收第二电压，并且（ii）响应于第二电压改变节点处的电流。

公开(公告)号：US06359468B1

公开(公告)日：2002-03-19

申请号：US09516865

申请日：2000-03-02

Applicant: James Park ,  Wei-Jen Huang ,  Tony Ngai ,  Bruce B. Pedersen

Inventor： James Park ,  Wei-Jen Huang ,  Tony Ngai ,  Bruce B. Pedersen

IPC: H03K19177

CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17792

Abstract: A programmable logic device is adapted to predict carry values in long-chain-carry logic configurations. In the most preferred embodiment, which functions in any long-carry-chain logic configuration, each logic region calculates a result for both values of the carry-in signal to that region, and when a carry signal for the group to which the region belongs reaches the region, the correct result in each region, and thence the correct carry-out for that group, are calculated and propagated. The carry-out terminal of one group is arranged to be adjacent to the carry-in terminal of the next group, to enhance carry propagation speed. In another embodiment, each region looks back two regions to predict the carry-in. In two additional embodiments, logic is provided to mathematically calculate the carry values.

Abstract translation: 可编程逻辑器件适用于预测长链进位逻辑配置中的进位值。 在最优选的实施例中，其在任何长承载链逻辑配置中起作用，每个逻辑区域计算对于该区域的进位信号的两个值的结果，以及当该区域所属的组的进位信号 到达该地区，每个地区的正确结果，然后计算和传播该组的正确进行。 一组的进位终端被布置成与下一组的进位终端相邻，以提高进位传播速度。 在另一个实施例中，每个区域回顾两个区域以预测携带。 在两个附加实施例中，提供逻辑以在数学上计算进位值。