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    Method and system for efficient use of a multi-dimensional sharing vector in a computer system
    41.
    发明授权
    Method and system for efficient use of a multi-dimensional sharing vector in a computer system 有权
    在计算机系统中有效利用多维共享向量的方法和系统

    公开(公告)号：US06915388B1

    公开(公告)日：2005-07-05

    申请号：US09910630

    申请日：2001-07-20

    申请人： William A. Huffman

    发明人： William A. Huffman

    IPC分类号： G06F12/06 ,  G06F12/08

    CPC分类号： G06F12/0826

    摘要： A multiprocessor computer system includes a plurality of processor nodes, a memory, and an interconnect network connecting the plurality of processor nodes to the memory. The memory includes a plurality of lines and a cache coherence directory structure. The plurality of lines includes a first line. The cache coherence directory structure includes a plurality of directory structure entries. Each directory structure entry includes processor pointer information indicating the processor nodes that have cached copies of the first line. The processor pointer information includes a plurality n of bit vectors, where n is an integer greater than one. The n bit vectors define a matrix having a number of locations equal to the product of the number of bits in each of the n bit vectors. The number of locations is greater than the number of processor nodes and each of the processor nodes is mapped to a corresponding one of the locations wherein the locations corresponding to the processor nodes are dispersed in the matrix in an at least partially noncontiguous manner.

    摘要翻译： 多处理器计算机系统包括多个处理器节点，存储器和将多个处理器节点连接到存储器的互连网络。 存储器包括多个行和高速缓存一致性目录结构。 多条线包括第一条线。 高速缓存一致性目录结构包括多个目录结构条目。 每个目录结构条目包括处理器指针信息，指示具有第一行的缓存副本的处理器节点。 处理器指针信息包括多个n个位向量，其中n是大于1的整数。 n位向量定义具有等于n位向量中的每一个中的位数的乘积的位置数的矩阵。 位置数量大于处理器节点的数量，并且每个处理器节点被映射到相应的一个位置，其中对应于处理器节点的位置以至少部分非连续的方式分散在矩阵中。

    Method and system for using high count invalidate acknowledgements in distributed shared memory systems
    42.
    发明授权
    Method and system for using high count invalidate acknowledgements in distributed shared memory systems 有权
    在分布式共享存储器系统中使用高计数无效确认的方法和系统

    公开(公告)号：US06718442B1

    公开(公告)日：2004-04-06

    申请号：US09910274

    申请日：2001-07-20

    申请人： William A. Huffman ,  Jeffrey S. Kuskin

    发明人： William A. Huffman ,  Jeffrey S. Kuskin

    IPC分类号： G06F1200

    CPC分类号： G06F12/0826

    摘要： A multiprocessor computer system includes a method and system of handling invalidation requests to a plurality of alias processors not sharing a line of memory in a computer system. A memory directory interface unit receives an invalidation request for a shared line of memory shared in a plurality of sharing processors. A superset of processors in the computer system that includes each of the sharing processors is determined that includes at least one alias processor not sharing the shared line of memory. An invalidation message is transmitted to each processor in the superset of processors. The number Na of alias processors in the superset of processors is determined and a superacknowledgement message is provided that is equivalent to acknowledging receipt of Na invalidation messages.

    摘要翻译： 多处理器计算机系统包括处理对在计算机系统中不共享存储器行的多个别名处理器的无效请求的方法和系统。 存储器目录接口单元接收对在多个共享处理器中共享的共享存储线路的无效请求。 确定包括每个共享处理器的计算机系统中的处理器的超集，其包括至少一个不共享共享存储器线的别名处理器。 无效消息被传送到处理器的超集中的每个处理器。 确定处理器超集中的别名处理器的数量Na，并且提供相当于确认接收到Na无效消息的超级确认消息。

    System and method for controlling split-level caches in a multi-processor system including data loss and deadlock prevention schemes
    43.
    发明授权
    System and method for controlling split-level caches in a multi-processor system including data loss and deadlock prevention schemes 失效
    用于控制多处理器系统中的分级缓存的系统和方法，包括数据丢失和死锁预防方案

    公开(公告)号：US5572704A

    公开(公告)日：1996-11-05

    申请号：US167005

    申请日：1993-12-15

    申请人： Joseph P. Bratt ,  John Brennan ,  Peter Y. Hsu ,  William A. Huffman ,  Joseph T. Scanlon ,  Steve Ciavagia

    发明人： Joseph P. Bratt ,  John Brennan ,  Peter Y. Hsu ,  William A. Huffman ,  Joseph T. Scanlon ,  Steve Ciavagia

    IPC分类号： G06F12/08 ,  G06F12/16

    CPC分类号： G06F12/0811

    摘要： A method for preventing data loss and deadlock in a multi-processor computer system wherein at least one processor in the computer system includes a split-level cache. The split-level cache has a byte-writable first-level and a word-writable second level. The method monitors the second level cache to determine if a forced atomic (FA) instruction is in a second level cache pipeline. If an FA instruction is determined to be in the second level cache pipeline, then interventions to the second level cache are delayed until the FA instruction exits the second level cache pipeline. In this manner data written by operation of cache memory access instruction that cause the interventions is not destroyed by the execution of the FA instruction, thereby preventing data loss. The method also monitors the second level cache pipeline to determine if a possible miss (PM) instruction is in the second level cache pipeline. If a PM instruction is determined to be in the second level cache pipeline, the FA instructions are prevented from entering the second level cache pipeline such that execution of interventions to the second level cache is not prevented when an instruction in the second level cache may be detained to process an intervention in its behalf, thereby preventing deadlock between processing units of the computer system.

    摘要翻译： 一种用于在多处理器计算机系统中防止数据丢失和死锁的方法，其中所述计算机系统中的至少一个处理器包括分级高速缓存。 分级缓存具有可写字节的第一级和可写字的第二级。 该方法监视第二级高速缓存以确定强制原子（FA）指令是否在二级高速缓存流水线中。 如果FA指令被确定在第二级高速缓存流水线中，则延迟到第二级高速缓存的干预，直到FA指令退出第二级高速缓存流水线。 以这种方式，通过执行FA指令不会破坏导致干预的高速缓冲存储器访问指令的操作所写入的数据，从而防止数据丢失。 该方法还监视第二级高速缓存流水线以确定可能的未命中（PM）指令是否在第二级高速缓存流水线中。 如果确定PM指令处于第二级高速缓存流水线中，则FA指令被阻止进入第二级高速缓存流水线，使得当第二级高速缓存中的指令可能为 被拘留以代表其进行干预，从而防止计算机系统的处理单元之间的僵局。

    Antistatic film bases and their process of manufacturing
    45.
    发明授权
    Antistatic film bases and their process of manufacturing 失效
    抗静电膜基材及其制造工艺

    公开(公告)号：US5238706A

    公开(公告)日：1993-08-24

    申请号：US905897

    申请日：1992-06-26

    申请人： William A. Huffman

    发明人： William A. Huffman

    IPC分类号： G03C1/89

    CPC分类号： G03C1/89

    摘要： The crosslinking of an antistatic polymer and crossliking agent on a flexible polymer abstract is enhanced by wrapping of the antistatic coated polymer substrate and heating said wrapped substrate to crosslink the coating.

    摘要翻译： 抗静电聚合物和交联剂在柔性聚合物摘要上的交联通过包裹抗静电涂布的聚合物基底并加热所述包裹的基底以交联涂层来增强。

    Substituted anthracene-type isotropic dyes for liquid crystal display devices
    46.
    发明授权
    Substituted anthracene-type isotropic dyes for liquid crystal display devices 失效
    用于液晶显示装置的取代的蒽类各向同性染料

    公开(公告)号：US4452511A

    公开(公告)日：1984-06-05

    申请号：US454706

    申请日：1982-12-30

    申请人： William A. Huffman

    发明人： William A. Huffman

    IPC分类号： C09B57/00 ,  C09K19/60 ,  G02F1/137 ,  G02F1/13 ,  C09K3/34

    CPC分类号： C09K19/60

    摘要： Certain substituted anthracene-type compounds have been found to be useful as isotropic dyestuffs in guest-host combinations with nematic, cholesteric and smectic liquid crystals and other well-known dichroic dyestuffs. By "isotropic" it is meant that the disclosed dyestuffs have optical order parameters (S) very close to zero. Use of the disclosed isotropic dyestuffs with additional well-known dichroic dyes in liquid crystal display devices, provides displays which alter between one colored state and another, depending upon the presence or absence of an electric field across the display.

    摘要翻译： 已经发现某些取代的蒽类化合物可用作客体 - 主体与向列型，胆甾醇型和近晶型液晶等众所周知的二色性染料的各向同性染料。 “各向同性”是指所公开的染料具有非常接近零的光学顺序参数（S）。 在液晶显示装置中使用所公开的各向同性染料与另外公知的二色性染料，根据显示器上是否存在电场，提供在一种着色状态和另一种着色状态之间改变的显示器。

    Electro-optical devices containing methine arylidene dyes
    48.
    发明授权
    Electro-optical devices containing methine arylidene dyes 失效
    含有次甲基亚芳基染料的电光装置

    公开(公告)号：US4105299A

    公开(公告)日：1978-08-08

    申请号：US786488

    申请日：1977-04-11

    申请人： William A. Huffman ,  Harvey A. Brown

    发明人： William A. Huffman ,  Harvey A. Brown

    IPC分类号： C09K19/60 ,  G02F1/13 ,  C09K3/34

    CPC分类号： C09K19/60

    摘要： Methine 4-nitro-arylidene dyes having certain substituents in the 2 position of the arylidene group are found to be pleochroic and to form guest-host combinations with dielectrically positive anisotropic nematic liquid crystals. These combinations are employed in electro-optical display devices.

    摘要翻译： 发现在亚芳基的2位具有某些取代基的甲基4-硝基 - 亚芳基染料是多色性的，并且与介电性各向异性向列型液晶形成客体 - 主体组合。 这些组合用于电光显示装置。

    Alignment and Ordering of Vector Elements for Single Instruction Multiple Data Processing
    50.
    发明申请
    Alignment and Ordering of Vector Elements for Single Instruction Multiple Data Processing 审中-公开
    用于单指令多数据处理的向量元素的对齐和排序

    公开(公告)号：US20110055497A1

    公开(公告)日：2011-03-03

    申请号：US12875268

    申请日：2010-09-03

    申请人： Timothy J. VAN HOOK ,  Peter Yan-Tek Hsu ,  William A. Huffman ,  Henry P. Moreton ,  Earl A. Killian

    发明人： Timothy J. VAN HOOK ,  Peter Yan-Tek Hsu ,  William A. Huffman ,  Henry P. Moreton ,  Earl A. Killian

    IPC分类号： G06F12/00

    CPC分类号： G06F9/30043 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30167 ,  G06F9/3885 ,  G06F9/3887

    摘要： The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register. Then, a subset of elements are selected from the first register and the second register. The elements from the subset are then replicated into the elements in the third register in a particular order suitable for subsequent SIMD vector processing.

    摘要翻译： 本发明提供用于SIMD处理的向量元素的对准和排序。 在用于SIMD处理的向量元素的对齐中，一个向量从存储器单元加载到第一寄存器中，另一个向量从存储器单元加载到第二寄存器中。 第一个向量包含要生成的对齐向量的第一个字节。 然后，确定指定对齐向量的第一个字节的起始字节。 接下来，从第一寄存器提取向量，并且从第一寄存器的第一字节的第一位开始的第二寄存器继续通过第二寄存器中的位。 最后，将所提取的矢量复制到第三寄存器中，使得第三寄存器包含对准用于SIMD处理的多个元素。 在用于SIMD处理的向量元素的排序中，将第一向量从存储器单元加载到第一寄存器中，并且将第二向量从存储器单元加载到第二寄存器中。 然后，从第一寄存器和第二寄存器中选择元件的子集。 然后将来自子集的元素以适合于随后的SIMD向量处理的特定顺序复制到第三寄存器中的元素中。