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公开(公告)号：US20090307425A1
公开(公告)日：2009-12-10
申请号：US12479403
申请日：2009-06-05
IPC分类号： G06F12/08
CPC分类号： G06F3/0689 , G06F3/0604 , G06F3/0619 , G06F3/0646 , G06F3/065 , G06F11/1076 , G06F2211/1028
摘要： Embodiments of systems and methods for routing commands to a distributed RAID system are disclosed. Specifically, embodiments may route a command to an appropriate data bank in a distributed RAID system, where each data bank has a set of associated storage media and executes a similar distributed RAID application. The distributed RAID applications on each of the data banks coordinate among themselves to distribute and control data flow associated with implementing a level of RAID in conjunction with data stored on the associated storage media of the data banks.
摘要翻译： 公开了将命令路由到分布式RAID系统的系统和方法的实施例。 具体地，实施例可以将命令路由到分布式RAID系统中的适当数据库，其中每个数据库具有一组关联的存储介质并执行类似的分布式RAID应用。 每个数据库上的分布式RAID应用程序在它们之间协调，以分配和控制与实现一级RAID相关联的数据流以及存储在数据库的相关联的存储介质上的数据。
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公开(公告)号：US5771359A
公开(公告)日：1998-06-23
申请号：US542708
申请日：1995-10-13
CPC分类号： G06F13/4059
摘要： A bridge for coupling two buses together utilizes a data buffer to act as a point of synchronization to provide effective data operations between the buses. The bridge includes master and slave capability on both buses and an arbiter for selecting between requests from bus masters on one bus. The data buffer includes a number of dual ported memories for write posting and read ahead operations. Each dual ported memory is allocated to a bus master of the one bus. The bridge allows data operations to each dual ported memory based on data or space availability of the memory. Simultaneous reading and writing capability on alternate buses is provided.
摘要翻译： 用于将两个总线耦合在一起的桥接器利用数据缓冲器作为同步点，以在总线之间提供有效的数据操作。 该桥梁包括两条总线上的主从功能和一个仲裁器，用于在一条总线上选择总线主机的请求。 数据缓冲器包括多个用于写入和预读操作的双端口存储器。 每个双端口存储器分配给一个总线的总线主机。 桥接器允许基于存储器的数据或空间可用性对每个双端口存储器进行数据操作。 提供备用总线同时的读写能力。
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公开(公告)号：US5809280A
公开(公告)日：1998-09-15
申请号：US542711
申请日：1995-10-13
CPC分类号： G06F7/78 , G06F12/125
摘要： A plurality of read-ahead FIFOs, each with an LRU replacement policy, is provided for enhancing buffer performance. The FIFO contains a plurality of adaptive buffer replacement counters to monitor usage statistics of the FIFOs and to identify one of the FIFOs as a refill candidate buffer in the event of a miss which requires new data to be brought into one of the FIFOs. Each FIFO has a hit detector and a flush detector for comparing the address of a data request from the bus master with the address stored by each buffer for indicating FIFO hit or invalidate operations. Each FIFO also has a buffer selector to provide data from the buffer selected by the hit detector to the bus master if the selected FIFO buffer has not been invalidated by the invalidate address comparator. The buffer selector otherwise transferring the requested data from the memory to the refill candidate buffer and presenting new data from the refill candidate buffer to the bus master. The FIFO has an invalidate address comparator coupled to the memory and the FIFOs to compares write addresses to the memory with each address of each FIFO to invalidate the FIFO buffer whose address tag matches the invalidate address to ensure data coherency.
摘要翻译： 提供了多个具有LRU替换策略的预读FIFO，用于增强缓冲器性能。 FIFO包含多个自适应缓冲器替换计数器，用于监视FIFO的使用统计，并且在错过的情况下，将FIFO中的一个识别为重新填充候选缓冲器，这需要将新数据带入FIFO之一。 每个FIFO具有命中检测器和冲洗检测器，用于将来自总线主机的数据请求的地址与每个缓冲器存储的地址进行比较，以指示FIFO命中或无效操作。 如果所选择的FIFO缓冲区未被无效地址比较器无效，则每个FIFO还具有缓冲选择器，用于将来自命中检测器选择的缓冲器的数据提供给总线主机。 缓冲器选择器否则将请求的数据从存储器传送到再填充候选缓冲器，并将新数据从补充候选缓冲器呈现给总线主机。 FIFO具有耦合到存储器和FIFO的无效地址比较器，以将写入地址与存储器与每个FIFO的每个地址进行比较，以使其地址标签与无效地址匹配的FIFO缓冲器无效，以确保数据一致性。
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公开(公告)号：US07472158B2
公开(公告)日：2008-12-30
申请号：US10396873
申请日：2003-03-26
申请人： William C. Galloway
发明人： William C. Galloway
CPC分类号： G06F13/387
摘要： SAS devices provide an OPEN frame when requesting a connection or path to a device. An initiator connection tag value, preferably a 16-bit value, is included in this OPEN frame by the initiator. The initiator connection tag value is included by the target device when the target device reconnects to the initiator. The initiator can use this smaller value in a table lookup to rapidly and easily identify the target device, without requiring decoding of the 64-bit WWN and without waiting to receive a frame containing a tag from the target and decoding that tag.
摘要翻译： 当请求设备的连接或路径时，SAS设备提供OPEN帧。 启动器连接标签值，优选16位值，由启动器包含在该OPEN帧中。 当目标设备重新连接到启动器时，启动器连接标签值由目标设备包含。 启动器可以在表查找中使用这个较小的值来快速和容易地识别目标设备，而不需要对64位WWN进行解码，并且不等待从目标接收包含标签的帧并对该标签进行解码。
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公开(公告)号：US06493785B1
公开(公告)日：2002-12-10
申请号：US09506709
申请日：2000-02-18
申请人： William C. Galloway
发明人： William C. Galloway
IPC分类号： G06F1336
CPC分类号： G06F13/4031
摘要： The present invention relates to a method of in-band communication, outside the standard SCSI communication protocol, between SCSI bus repeaters and initiator devices. The present invention implements the communication mode during the message phase of the SCSI protocol and allows initiators on a SCSI bus to determine the number, location and status of SCSI repeaters accessible on the SCSI bus.
摘要翻译： 本发明涉及在标准SCSI通信协议之外的SCSI总线中继器和启动器设备之间的带内通信的方法。 本发明在SCSI协议的消息阶段实现通信模式，并且允许SCSI总线上的发起者确定在SCSI总线上可访问的SCSI中继器的数量，位置和状态。
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公开(公告)号：US5761527A
公开(公告)日：1998-06-02
申请号：US811321
申请日：1997-03-04
CPC分类号： G06F3/0607 , G06F11/325 , G06F3/0653 , G06F3/0676 , G11B33/10 , G06F11/3485 , G11B31/00
摘要： A computer system which includes a circuit to monitor the PCI bus master grant lines and provide a disk drive activity signal if an appropriate grant line is activated. The PCI bus master grant lines are combined with mask signals, so that the grant lines not associated with a PCI bus master such as a SCSI controller are ignored. If an unmasked grant line is activated, a down counter is loaded. While the counter is at a non-zero value, a disk drive activity signal is provided. This disk drive activity signal is combined with other disk drive activity signals to drive the disk drive activity LED.
摘要翻译： 一种计算机系统，其包括用于监视PCI总线主机授权线路的电路，并且如果适当的授权线路被激活则提供磁盘驱动器活动信号。 PCI总线主机授权线路与掩码信号组合，从而忽略与PCI总线主机（如SCSI控制器）无关的授权线路。 如果未屏蔽授权行被激活，则加载递减计数器。 当计数器处于非零值时，提供磁盘驱动器活动信号。 此磁盘驱动器活动信号与其他磁盘驱动器活动信号相结合，以驱动磁盘驱动器活动LED。
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公开(公告)号：US06654829B2
公开(公告)日：2003-11-25
申请号：US10260932
申请日：2002-09-30
IPC分类号： G06F1314
CPC分类号： H05K7/1459
摘要： In a computer system having redundant SCSI controllers cards, a SCSI controller interface for receiving multiple interchangeable SCSI controller cards is configured so that the data bus paths between each of the SCSI controller slots and the controller circuitry do not cross.
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公开(公告)号：US5944798A
公开(公告)日：1999-08-31
申请号：US802673
申请日：1997-02-19
IPC分类号： H04L12/433 , G06F11/00
CPC分类号： H04L12/433
摘要： A computer system with a plurality of devices compatible with the Fibre Channel Protocol. The computer system is provided with the capability to recover from a loop hang condition resulting from an unresponsive communication link in an Arbitrated Loop. This capability is realized by providing a sense mechanism for detecting a no-change condition in the states associated with a controller arranged in the Arbitrated Loop.
摘要翻译： 具有与光纤通道协议兼容的多个设备的计算机系统。 计算机系统具有从仲裁环路中无响应的通信链路导致的循环挂起状况恢复的能力。 该能力通过提供用于检测与布置在仲裁环路中的控制器相关联的状态中的无变化状态的感测机制来实现。
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公开(公告)号：US5816673A
公开(公告)日：1998-10-06
申请号：US730470
申请日：1996-10-11
摘要： A modular computer chassis constructed with a center pluggable interface adapted for the modular mounting of components on opposite sides thereof. The chassis includes frontal and rear regions which are open and adapted for receipt of modular computer components therein for direct coupling to the center pluggable interface. An isolation frame is also provided within the chassis for physically and electrically isolating select components therein one from the other. A slidable mounting array is also provided for facilitating flexibility in the mounting of half height and one-third height disk drives adjacent to the center pluggable interface for flexibility in the design and utilization of the chassis of the present invention.
摘要翻译： 一个模块化的计算机机箱，其中央可插拔接口适用于组件安装在其相对侧上。 底盘包括前部区域和后部区域，该区域是敞开的并且适于在其中接收模块化计算机部件，用于直接联接到中心可插接口。 隔离框架还设置在底盘内，用于物理和电气隔离其中一个选择部件。 还提供了可滑动的安装阵列，以便于在靠近中心可插拔接口的情况下安装半高和三分之一高度磁盘驱动器的灵活性，以便灵活地设计和利用本发明的底盘。
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公开(公告)号：US06636921B1
公开(公告)日：2003-10-21
申请号：US09507278
申请日：2000-02-18
IPC分类号： G06F1300
CPC分类号： G06F13/404
摘要： The present invention relates to a repeater circuit for providing effective point-to-point coupling between terminated Small Computer System Interface (SCSI) bus segments. The repeater circuit has an enable input and can perform SCSI address translation to map SCSI addresses from a narrow SCSI bus to high SCSI addresses on a wide SCSI bus.
摘要翻译： 本发明涉及一种用于在终止的小型计算机系统接口（SCSI）总线段之间提供有效的点对点耦合的中继器电路。 中继器电路具有使能输入，并且可以执行SCSI地址转换，将SCSI地址从窄SCSI总线映射到宽SCSI总线上的高SCSI地址。
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