公开(公告)号：US4523274A

公开(公告)日：1985-06-11

申请号：US250644

申请日：1981-04-03

申请人： Yasushi Fukunaga ,  Tadaaki Bandoh

发明人： Yasushi Fukunaga ,  Tadaaki Bandoh

IPC分类号： G06F15/16 ,  G06F1/12 ,  G06F13/42 ,  G06F15/177

CPC分类号： G06F13/4217

摘要： There is disclosed a data processing system comprising a plurality of processors having different processing speeds and connected with a synchronous common bus, the processors being able to access a common memory connected with the common bus.A high frequency master clock signal generating means is provided in common for the processors of the system and the respective processors can be operated with the associated different machine cycles determined in accordance with the corresponding different processing speeds by frequency-dividing the master clock signal. In addition, each processor can be operated with different machine cycles depending on its operations.

摘要翻译： 公开了一种数据处理系统，包括具有不同处理速度并与同步公共总线连接的多个处理器，处理器能够访问与公共总线连接的公共存储器。 为系统的处理器共同提供高频主时钟信号发生装置，并且可以通过对主时钟信号进行分频，根据相应的不同处理速度确定相关的不同机器周期来操作相应的处理器。 此外，每个处理器可以根据其操作以不同的机器周期进行操作。

公开(公告)号：US4454578A

公开(公告)日：1984-06-12

申请号：US265168

申请日：1981-05-19

申请人： Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hideo Maejima

发明人： Hidekazu Matsumoto ,  Tadaaki Bandoh ,  Hideo Maejima

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/318 ,  G06F9/34 ,  G06F9/42 ,  G06F9/36

CPC分类号： G06F9/30192 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3822 ,  G06F9/3889

摘要： A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations is disclosed. An instruction fetch unit includes an instruction buffer for prefetching and retaining instructions from a memory and alignment means for aligning the instructions from the instruction buffer such that the instruction includes at least one operand specifier in one machine cycle, and provides it to a decoding unit. The decoding unit includes an operation code decoder and two operand specifier decoders to decode two operand specifiers simultaneously when the last operand specifier is a register designation mode. Each of the units executes instructions in a pipelined fashion and processes operands in a pipelined fashion.

摘要翻译： 一种用于执行可变长度指令的数据处理单元，其中用于指定操作数的寻址模式的操作数说明符与用于确定操作的操作代码无关。 指令提取单元包括用于从存储器预取和保存指令的指令缓冲器以及用于对准来自指令缓冲器的指令的对准装置，使得指令在一个机器周期中包括至少一个操作数说明符，并将其提供给解码单元。 解码单元包括操作码解码器和两个操作数说明符解码器，以在最后一个操作数说明符是寄存器指定模式时同时解码两个操作数说明符。 每个单元以流水线方式执行指令，并以流水线方式处理操作数。