公开(公告)号：US20050171989A1

公开(公告)日：2005-08-04

申请号：US10907943

申请日：2005-04-21

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: G06F17/10 ,  H03H17/02 ,  H03H17/06

CPC classification number: H03H17/06 ,  H03H17/0229 ,  H03H2017/0072

Abstract: A digital filter is designed by combining unit filters (L10′, H10′) having a predetermined asymmetric numerical sequence as filter coefficients (H1 to H3). Thus, it is possible to automatically obtain a desired digital filter coefficient only by combining the unit filter. Moreover, a symmetric numerical sequence {−1, 0, 9, 16, 9, 0, −1}/32 is divided at the center into two parts and one of them is used as the asymmetric filter coefficients (H1 to H3). This reduces the number of taps required for the digital filter designed, eliminates use of a window function, and prevents generation of a discretization error in the filter characteristic obtained.

Abstract translation: 通过将具有预定的非对称数字序列的单元滤波器（L 10'，H 10'）组合为滤波器系数（H 1至H 3）来设计数字滤波器。 因此，可以通过组合单位滤波器来自动获得期望的数字滤波器系数。 此外，将对称数字序列{-1,0,9,16,9,0-1} / 32在中心分成两部分，其中一个用作不对称滤波器系数（H 1至H 3 ）。 这减少了设计的数字滤波器所需的抽头数量，消除了使用窗口功能，并且防止了所获得的滤波器特性中的离散化误差的产生。

公开(公告)号：US20050111562A1

公开(公告)日：2005-05-26

申请号：US10979733

申请日：2004-11-03

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: G10L19/14 ,  H03G5/00 ,  H03H17/06 ,  H04K1/10

CPC classification number: G10L19/26 ,  H03G5/005 ,  H03H17/06

Abstract: A waveform of a desired frequency characteristic is input as a numeric value string and is subjected to reverse FFT so as to obtain a filter coefficient group. Thus, without having any expert knowledge, only by inputting a waveform of a desired frequency characteristic as an image, it is possible to easily design a first FIR filter constituting a tone quality adjustment device. Moreover, by performing a predetermined calculation on the numeric value string input and performing a reverse FFT to the result, it is possible to easily design a second FIR filter having a frequency characteristic symmetric to the first FIR filter with respect to the gain reference value as an axis.

Abstract translation: 将期望的频率特性的波形作为数值串输入，并进行逆FFT以获得滤波器系数组。 因此，没有任何专业知识，只有通过输入期望的频率特性的波形作为图像，可以容易地设计构成音质调整装置的第一FIR滤波器。 此外，通过对数值串串输入进行预定的计算并对结果执行反向FFT，可以容易地将具有与第一FIR滤波器对称的频率特性的第二FIR滤波器相对于增益参考值设计为 一个轴。

公开(公告)号：US06894966B1

公开(公告)日：2005-05-17

申请号：US09914505

申请日：2000-05-11

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: G06F17/17 ,  G06T3/40 ,  H03H17/02 ,  H03H17/06 ,  G11B5/09

CPC classification number: G06T3/4007 ,  G06F17/17 ,  G06F17/175

Abstract: An interpolation circuit capable of performing interpolation operation with a simple constitution. A 16-times oversampling from discrete data is performed by D frip-frops 4, 5. A first convolution operation is performed by D frip-frops 4 through 11 and an adder 12, on the result of which a second convolution operation is performed by D frip-frops 13 through 20 and an adder 21. Data interpolated along a quadratic function curve interpolating the discrete data is obtained from the adder 21.

Abstract translation: 一种能够以简单的结构执行插值操作的插值电路。 离散数据的16次过采样由D frip-frops 4,5执行。 第一卷积运算由D frip-frops 4至11和加法器12执行，其结果是由D frip-frops 13至20和加法器21执行第二卷积运算。 从加法器21获得沿插补离散数据的二次函数曲线插入的数据。

公开(公告)号：US06785644B2

公开(公告)日：2004-08-31

申请号：US10319466

申请日：2002-12-16

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: G10L1106

CPC classification number: G10L25/90 ,  G10L19/0204 ,  G10L19/09

Abstract: With respect to data having periodicity to be compressed, windows of the same size are set for every two sections according to an interval of peaks appearing substantially periodically and processing for sorting sample data alternately among the set windows of the same size is sequentially performed, whereby a frequency of data having periodicity is replaced with an approximately half frequency without damaging reproducibility to original data at all to make it possible to apply compression processing to data of the replaced low frequency. If this sorting processing is applied to compression processing having a characteristic that a compression ratio is not increased in a high-frequency region, it becomes possible to improve a compression ratio without damaging a quality of reproduced data by decompression at all.

Abstract translation: 对于具有要压缩的周期的数据，根据基本上周期性地出现的峰值的间隔，对于每两个部分设置相同大小的窗口，并且顺序地执行用于在相同大小的设置窗口之间交替分类样本数据的处理，由此 具有周期性的数据的频率被大约一半的频率代替，而不损害对原始数据的再现性，使得可以对被替换的低频的数据应用压缩处理。 如果该分类处理被应用于具有在高频区域中不增加压缩比的特性的压缩处理，则可以提高压缩比，而不损害通过解压缩的再现数据的质量。

公开(公告)号：US06448918B1

公开(公告)日：2002-09-10

申请号：US09890538

申请日：2001-07-31

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: H03M166

CPC classification number: H03M3/508

Abstract: It is object to provide a digital-to-analog converter capable of generating an output waveform having less distortion without increasing the operating speed of components. A D/A converter comprises a multiplying section 1, four data holding sections 2-1 through 2-4, four data selectors 3-1 through 3-4, an adding section 4, a D/A converter 5, and two integrating circuits 6-1 and 6-2. Input data is multiplied by four multiplicators by the multiplying section 1, and the four multiplication results are held, as one set, in the data holding sections. The data selectors read out the data held in the four data holding sections in a predetermined order and generate step function data. The adding section adds the values of the step functions outputted from the four data selectors. Furthermore, a stepwise analog voltage corresponding to the sum is generated by the D/A converter 5 and integrated twice by means of the two integrating circuits 6-1 and 6-2.

Abstract translation: 目的在于提供一种能够产生具有较小失真的输出波形的数模转换器，而不增加部件的运行速度。 AD / A转换器包括乘法部分1，四个数据保持部分2-1至2-4，四个数据选择器3-1至3-4，加法部分4，D / A转换器5和两个积分电路6 -1和6-2。 输入数据由乘法部分1乘以四个乘法器，四个相乘结果作为一组保存在数据保持部分中。 数据选择器以预定顺序读出保存在四个数据保持部分中的数据，并生成步骤功能数据。 添加部分添加从四个数据选择器输出的步骤功能的值。 此外，与D / A转换器5产生对应于和的逐步模拟电压，并通过两个积分电路6-1和6-2集成两次。

公开(公告)号：US06411238B1

公开(公告)日：2002-06-25

申请号：US09743456

申请日：2001-01-09

Applicant: Yukio Koyanagi ,  Kazuo Toraichi

Inventor： Yukio Koyanagi ,  Kazuo Toraichi

IPC: H03M106

CPC classification number: H03M1/0872 ,  H03M1/66

Abstract: A digital-to-analog converter for generating output waveforms with less distortion without the need for high-speed components. The digital-to-analog converter comprises four data holding sections, four step function generators, an adding section, a D/A converter, two integrators and a timing controller. Four digital data successively inputs are held in the data holding sections, respectively, and the step function generators generate step function whose values corresponding to the held data. The adding section sums the step functions generated in the step function generators, and the D/A converter generates the analog stepwise voltage corresponding to the summed value. The two integrators integrate this combined waveform two times, thus producing a continuous analog voltage that connects the input digital data smoothly.

Abstract translation: 一个数模转换器，用于在不需要高速组件的情况下生成输出波形较少的失真。 数模转换器包括四个数据保持部分，四个阶梯函数发生器，一个加法部分，一个D / A转换器，两个积分器和一个定时控制器。 四个数字数据连续输入分别保存在数据保持部分中，步进函数发生器产生与保持数据相对应的值的阶梯函数。 加法部分对步进函数发生器中产生的阶跃函数求和，D / A转换器产生与求和值对应的模拟步进电压。 两个集成商将这种组合波形整合在一起，从而产生连续的模拟电压，从而平滑地连接输入数字数据。

公开(公告)号：US4593414A

公开(公告)日：1986-06-03

申请号：US568240

申请日：1983-12-14

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: G04G15/00 ,  G05B19/02 ,  H03J7/18 ,  H04B1/06 ,  H04N5/44 ,  H04B1/16

CPC classification number: G04G15/006 ,  H03J7/18

Abstract: A system for obviating the special operation needed for storing a program in memories in a channel selecting system used in television sets, etc., which is adapted to make the control for selecting specified channels at specified times, following a program which has been preliminarily stored in the memories, by writing into the memories from the channel control means the state of channel selection unmodified, as the program, which is based on the channel selecting operation actually performed by the user, using the commanding means during normal real time operation, as a way of storing the program in the memories.

Abstract translation: PCT No.PCT / JP83 / 00120 Sec。 371日期：1983年12月14日第 102（e）1983年12月14日日期PCT提交1983年4月15日PCT公布。 出版物WO83 / 03726 日期：1983年10月27日。一种用于消除用于在电视机等中使用的频道选择系统中的存储器中的程序所需的特殊操作的系统，其适于在特定时间进行用于选择指定频道的控制 已经预先存储在存储器中的程序通过使用命令装置将来自信道控制装置的未经修改的信道选择状态作为基于用户实际执行的信道选择操作的程序写入存储器， 在正常的实时操作期间，作为将程序存储在存储器中的一种方式。

公开(公告)号：US4209775A

公开(公告)日：1980-06-24

申请号：US944898

申请日：1978-09-22

Applicant: Kazumi Kawashima ,  Yukio Koyanagi

Inventor： Kazumi Kawashima ,  Yukio Koyanagi

IPC: H03M1/82 ,  H03M1/00 ,  H03K13/02

CPC classification number: H03M1/504 ,  H03M1/0631

Abstract: A D-A converter for converting a digital signal to a duty factor of a pulse train signal and for averaging the pulse signal by a low-pass filter to convert it to an analog signal is disclosed. A plurality of pulses which are to be selected in accordance with the input digital signal comprise a plurality of basic pulses of different phases and pulse widths derived by frequency division and auxiliary basic pulses which occur at a cycle period which is at least twice as long as a repetition cycle period of the basic pulses. The basic pulses are selected by high order bits of the digital signal while the auxiliary basic pulses are selected by low order bits of the digital signal to produce an output pulse train signal a duty factor of which changes in accordance with the digital signal. The pulse train signal is then averaged to convert it to an analog signal.

Abstract translation: 公开了一种D-A转换器，用于将数字信号转换为脉冲序列信号的占空系数，并通过低通滤波器对脉冲信号进行平均以将其转换为模拟信号。 要根据输入数字信号选择的多个脉冲包括通过分频和辅助基本脉冲导出的不同相位和脉冲宽度的多个基本脉冲，其发生在周期为至少两倍于 基本脉冲的重复循环周期。 基本脉冲由数字信号的高位选择，而辅助基本脉冲由数字信号的低位选择，以产生根据数字信号而改变的占空因数的输出脉冲序列信号。 然后将脉冲序列信号进行平均以将其转换为模拟信号。

公开(公告)号：US4117476A

公开(公告)日：1978-09-26

申请号：US764761

申请日：1977-02-02

Applicant: Yukio Koyanagi

Inventor： Yukio Koyanagi

IPC: H03M1/82 ,  H03M1/00 ,  H03K13/20

CPC classification number: H03M1/822

Abstract: Disclosed is a digital-to-analog converter wherein a counter comprising a number of n - m (where n > m) flip-flops is so arranged that an m-bit and (n - m)-bit outputs may be alternately derived, weighted and added to derive an n-bit output which in turn is smoothed to deliver a DC output.