公开(公告)号：US20120141137A1

公开(公告)日：2012-06-07

申请号：US13301149

申请日：2011-11-21

申请人： Kazuyuki Tajima ,  Tomohiro Hashiguchi

发明人： Kazuyuki Tajima ,  Tomohiro Hashiguchi

IPC分类号： H04B10/18 ,  H04B10/12

CPC分类号： H04B10/25253

摘要： A dispersion compensation design system includes a changing unit setting a changed value for the amount of dispersion compensation for a span connecting nodes constituting an optical network; a path classification unit determining whether respective paths in the optical network are capable of transmission with the changed value and classifying one or more of the paths as second category paths based on the determination results; an updating unit updating the amount of dispersion compensation with the changed value if the number of the second category paths in the latest classification result is less than the number of the second category paths in the retained previous classification result; and a repeating unit that, if not all of the paths in the optical network are capable of transmission, prevents use of combinations of amounts of dispersion compensation applied to the spans in the second category paths in the latest classification result.

摘要翻译： 色散补偿设计系统包括：改变单元，设置用于构成光网络的节点的跨度的色散补偿量的变化值; 路径分类单元，确定光网络中的相应路径是否能够以改变的值传输，并且基于确定结果将一个或多个路径分类为第二类别路径; 如果最新分类结果中的第二类别路径的数量少于所保留的先前分类结果中的第二类别路径的数量，则更新单元用改变的值更新色散补偿量; 以及如果不是全部光网络中的路径能够传输的重复单元，则防止在最新分类结果中使用在第二类别路径中应用于跨度的色散补偿量的组合。

公开(公告)号：US20080164913A1

公开(公告)日：2008-07-10

申请号：US11979679

申请日：2007-11-07

申请人： Manabu Hirata ,  Takashi Taya ,  Kazuyuki Tajima

发明人： Manabu Hirata ,  Takashi Taya ,  Kazuyuki Tajima

IPC分类号： G01R19/00

CPC分类号： H03F3/45

摘要： A peak-hold circuit includes a differential amplifier having first and second transistors as a differential pair, the first transistor receiving an input signal at its gate, a third transistor connected between a first power supply and an output node connecting a gate of the second transistor, connectivity of the third transistor being controlled by the output of the differential amplifier, a capacitor for holding a peak voltage, connected between the output node and a second power supply, a resistor for discharging, which is connected in parallel to the capacitor, and a fourth transistor connected to the first transistor in parallel, the fourth transistor receiving at its gate an a reference voltage for limiting a voltage.

摘要翻译： 峰值保持电路包括具有作为差分对的第一和第二晶体管的差分放大器，第一晶体管在其栅极接收输入信号，连接在第一电源和连接第二晶体管的栅极的输出节点之间的第三晶体管 连接在输出节点和第二电源之间的用于保持峰值电压的电容器，与电容器并联连接的用于放电的电阻器，以及 第四晶体管并联连接到第一晶体管，第四晶体管在其栅极处接收用于限制电压的参考电压。

公开(公告)号：US20050265356A1

公开(公告)日：2005-12-01

申请号：US11050152

申请日：2005-02-03

申请人： Kenichi Kawarai ,  Hiroyuki Kaneko ,  Kazuyuki Tajima ,  Kou Takatori

发明人： Kenichi Kawarai ,  Hiroyuki Kaneko ,  Kazuyuki Tajima ,  Kou Takatori

IPC分类号： H04L12/46 ,  H04L12/56

CPC分类号： H04L45/26 ,  H04L12/4641 ,  H04L45/02

摘要： An arbitrary node that belongs to a virtual LAN sends a request packet including a count value indicating the number of communication hops across nodes to each of its adjacent nodes that belong to the virtual LAN and are adjacent. Upon receiving the request packet, each of the adjacent nodes sends the request packet in which the count value is incremented or decremented, as predetermined, to each of its adjacent nodes that belong to the virtual LAN and are adjacent to the node, excluding a sender of the request packet received, and sends a reply packet including the sender's address (sender address), an address of the node that is a replying node (replying node address), and the count value to a given return destination. The return destination collects reply packets sent thereto and keeps track of the topology of the nodes constituting the virtual LAN from information contained in the reply packets.

摘要翻译： 属于虚拟LAN的任意节点将包含指示跨越节点的通信跳数的计数值的请求分组发送给属于虚拟LAN并且相邻的每个相邻节点。 在接收到请求分组时，每个相邻节点将计数值按预定的顺序递增或递减的请求分组发送到属于虚拟LAN并且与该节点相邻并且与该节点相邻的每个相邻节点，不包括发送者 并且发送包括发送方地址（发送方地址）的应答分组，作为应答节点的节点的地址（回复节点地址），并将计数值发送给给定的返回目的地。 返回目的地收集发送到其中的应答分组，并且从包含在应答分组中的信息中跟踪构成虚拟LAN的节点的拓扑。

公开(公告)号：US07853226B2

公开(公告)日：2010-12-14

申请号：US11979679

申请日：2007-11-07

申请人： Manabu Hirata ,  Takashi Taya ,  Kazuyuki Tajima

发明人： Manabu Hirata ,  Takashi Taya ,  Kazuyuki Tajima

IPC分类号： H04B1/16

CPC分类号： H03F3/45

摘要： A peak-hold circuit includes a differential amplifier having first and second transistors as a differential pair, the first transistor receiving an input signal at its gate, a third transistor connected between a first power supply and an output node connecting a gate of the second transistor, connectivity of the third transistor being controlled by the output of the differential amplifier, a capacitor for holding a peak voltage, connected between the output node and a second power supply, a resistor for discharging, which is connected in parallel to the capacitor, and a fourth transistor connected to the first transistor in parallel, the fourth transistor receiving at its gate an a reference voltage for limiting a voltage.

摘要翻译： 峰值保持电路包括具有作为差分对的第一和第二晶体管的差分放大器，第一晶体管在其栅极接收输入信号，连接在第一电源和连接第二晶体管的栅极的输出节点之间的第三晶体管 连接在输出节点和第二电源之间的用于保持峰值电压的电容器，与电容器并联连接的用于放电的电阻器，以及 第四晶体管并联连接到第一晶体管，第四晶体管在其栅极处接收用于限制电压的参考电压。

公开(公告)号：US20060197610A1

公开(公告)日：2006-09-07

申请号：US11346296

申请日：2006-02-03

申请人： Manabu Hirata ,  Yoichi Fueki ,  Kazuyuki Tajima

发明人： Manabu Hirata ,  Yoichi Fueki ,  Kazuyuki Tajima

IPC分类号： H03L7/00

CPC分类号： H03L7/0995

摘要： A voltage controlled oscillator which performs an oscillating operation at a frequency corresponding to a control voltage, includes a voltage-current converter circuit which converts the control voltage to a control current corresponding to a voltage value thereof, and a ring oscillator through which an operating current corresponding to the control current generated by the voltage-current converter circuit is caused to flow, and which oscillates at a frequency corresponding to a current value thereof. The voltage-current converter circuit has a voltage-voltage converting circuit which inputs the control voltage therein and converts the same to a control current corresponding to the voltage value thereof, and an offset current generating circuit which adds a constant current to the control current.

摘要翻译： 以与控制电压对应的频率进行振荡动作的压控振荡器包括：电压 - 电流转换器电路，其将控制电压转换为对应于其电压值的控制电流;以及环路振荡器，通过该振荡器，工作电流 与由电压 - 电流转换器电路产生的控制电流相对应地流过，并以与其电流值对应的频率振荡。 电压 - 电流转换器电路具有输入其中的控制电压的电压 - 电压转换电路，并将其转换成与其电压值相对应的控制电流，以及将恒定电流加到控制电流上的偏移电流产生电路。

公开(公告)号：US06658009B1

公开(公告)日：2003-12-02

申请号：US09460917

申请日：1999-12-14

申请人： Haruo Yamashita ,  Masatake Miyabe ,  Tomohiro Shinomiya ,  Kazuyuki Tajima ,  Masamichi Kasa

发明人： Haruo Yamashita ,  Masatake Miyabe ,  Tomohiro Shinomiya ,  Kazuyuki Tajima ,  Masamichi Kasa

IPC分类号： H04L1256

CPC分类号： H04Q11/0066 ,  H04Q11/04 ,  H04Q2011/0064 ,  H04Q2011/0094 ,  H04Q2213/1301 ,  H04Q2213/13103 ,  H04Q2213/13174 ,  H04Q2213/13176 ,  H04Q2213/13204 ,  H04Q2213/13251 ,  H04Q2213/13349

摘要： In a system where a plurality of terminal units are connected to a network unit via an optical transmission line and packets are transmitted in units of cells according to polling information, polling request information including the number of variable-length packets stored in the buffer of each of the terminal unit, the number of cells composing each variable-length packet and the number of remaining cells of a packet being read is created, polling information corresponding to a time slot allocated according to the polling request information is transmitted from the shared band control unit of the network unit, and bands are allocated to the plurality of terminal units.

摘要翻译： 在多个终端单元通过光传输线路连接到网络单元并且根据轮询信息以小区为单位发送分组的系统中，轮询请求信息包括存储在每个缓冲器中的可变长度分组的数量 ，构成每个可变长度分组的单元数目和正在读取的分组的剩余单元数，从共享频带控制中发送与根据轮询请求信息分配的时隙相对应的轮询信息 单元，并且将频带分配给多个终端单元。

公开(公告)号：US5257311A

公开(公告)日：1993-10-26

申请号：US876417

申请日：1992-04-30

申请人： Hidetoshi Naito ,  Masaaki Kawai ,  Hisako Watanabe ,  Yuji Takizawa ,  Kazuyuki Tajima ,  Haruo Yamashita

发明人： Hidetoshi Naito ,  Masaaki Kawai ,  Hisako Watanabe ,  Yuji Takizawa ,  Kazuyuki Tajima ,  Haruo Yamashita

IPC分类号： H04Q3/52 ,  H04L12/26 ,  H04L12/70 ,  H04Q3/00 ,  H04Q11/04 ,  H04L9/00

CPC分类号： H04L49/3009 ,  H04L12/2697 ,  H04L43/50 ,  H04L49/3081 ,  H04L49/555 ,  H04Q11/0478 ,  H04L2012/5628 ,  H04L2012/5652 ,  H04L49/30

摘要： A system for monitoring an ATM cross-connecting apparatus by inputting a test cell through a path for a main signal into the ATM cross-connecting apparatus, and examining the cell after the cell passed through the ATM cross-connecting apparatus. An initial value of a PN sequence and the PN sequence generated based on the initial bit sequence is written in the test cell before inputting to the ATM cross-connecting apparatus. When examining the test cell, the initial bit sequence and the PN sequence are read from the cell, a PN sequence is generated based on the initial bit sequence, and the generated pseudo-noise sequence is then compared with the PN sequence read from the test cell to detect an error in the test cell. In addition, a bit pattern indicating a primitive polynomial to generate the PN sequence may be written in the test cell. In this case, the bit pattern is used for generating the PN sequence when examining the test cell. Further, the same VPI values may be written in both the header and the information field of the test cell before inputting the cell to the ATM cross-connecting apparatus, and the VPI value in the information field is compared with a VPI value in the header of the test cell when examining the test cell.

公开(公告)号：US06662353B2

公开(公告)日：2003-12-09

申请号：US10084349

申请日：2002-02-28

申请人： Junichi Yamamoto ,  Sachio Henmi ,  Shigemitsu Fujisawa ,  Masanobu Sakurai ,  Kazuyuki Tajima ,  Fumio Kobayashi ,  Masaaki Ueno

发明人： Junichi Yamamoto ,  Sachio Henmi ,  Shigemitsu Fujisawa ,  Masanobu Sakurai ,  Kazuyuki Tajima ,  Fumio Kobayashi ,  Masaaki Ueno

IPC分类号： G06F1750

CPC分类号： G06F17/50 ,  G06Q30/0283 ,  H05K3/0005

摘要： The present invention relates to an estimation system that can provide a highly reliable estimation result when the estimation system estimates person-hours required to prepare a film pattern for a circuit to be printed on a board. Upon receiving design conditions from a cline machine, a reference pin calculator of the estimation system calculates a number of reference pins on the basis of a total number of pins extending from parts to be integrated on the printed circuit board and a special specification requirement to be applied to the printed circuit. An additional pin calculator calculates a number of additional pins on the basis of a signal line wiring method. A total estimated pin calculator corrects a sum of the reference pins and the additional pins on the basis of design difficulty, which is determined from a number of signal layers to be made in the printed circuit, a number of signal lines arrangeable between adjacent pins and a pin density, to calculate a total estimated number of pins. A person-hour calculator calculates person-hours required to prepare a pattern film of the printed circuit by dividing the total estimated number of the pins by an average number of pins handleable by a design engineer per a unit time.

摘要翻译： 本发明涉及一种估计系统，当估计系统估计准备要印刷在电路板上的电路的胶片图案所需的人工时间时，可以提供高可靠性的估计结果。 在收到设计条件的情况下，估计系统的参考引脚计算器基于从要集成在印刷电路板上的部件延伸的引脚总数来计算多个参考引脚，并且需要特殊规范要求 应用于印刷电路。 额外的引脚计算器根据信号线布线方法计算多个附加引脚。 总估计引脚计算器基于设计难度来校正参考引脚和附加引脚的总和，该设计难度由在印刷电路中制造的信号层数量，可布置在相邻引脚之间的多个信号线和 一个针脚密度，来计算一个总的估计引脚数。 人员计时器通过将总计估计的引脚数除以设计工程师每单位时间可处理的平均引脚数来计算准备印刷电路图案胶片所需的人工小时数。

公开(公告)号：US08676947B2

公开(公告)日：2014-03-18

申请号：US12474411

申请日：2009-05-29

申请人： Kazuyuki Tajima ,  Shinya Kano

发明人： Kazuyuki Tajima ,  Shinya Kano

IPC分类号： G06F15/173

CPC分类号： H04L69/14 ,  H04L45/125 ,  H04L45/22 ,  H04L47/70 ,  H04L47/726 ,  H04L69/40 ,  Y02D50/30

摘要： A resource reservation apparatus reserving a resource on a second and third route connecting a start with end node of the first route over a network having a resource on a first route, includes a resource controller for defining a fourth route including a link obtained by excluding a common link between the first and second route and between the first and third route from a link included in the first, second or third route, a message generator for generating a message used for reserving a resource of the link included in the fourth route and transmitting the message to a node on the fourth route, and a message processor for transmitting a message used for generating the second and third route from the resource on the first route and on the fourth route reserved by the message generator to a node included in the second or third route.

摘要翻译： 一种资源预留装置，在通过具有第一路径的资源的网络上连接起始于第一路由的终端的第二和第三路由上的资源包括资源控制器，用于定义包括通过排除 在第一和第二路由之间以及从包括在第一，第二或第三路由中的链路的第一和第三路由之间的公共链路，用于生成用于保留包括在第四路由中的链路的资源的消息的消息生成器， 向第四路由上的节点发送的消息，以及消息处理器，用于从第一路由上的资源和由消息生成器预留的第四路由发送用于生成第二和第三路由的消息到包括在第二路由中的节点 或第三条路线。

公开(公告)号：US08027262B2

公开(公告)日：2011-09-27

申请号：US11050152

申请日：2005-02-03

申请人： Kenichi Kawarai ,  Hiroyuki Kaneko ,  Kazuyuki Tajima ,  Kou Takatori

发明人： Kenichi Kawarai ,  Hiroyuki Kaneko ,  Kazuyuki Tajima ,  Kou Takatori

IPC分类号： H04J3/14

CPC分类号： H04L45/26 ,  H04L12/4641 ,  H04L45/02

摘要： An arbitrary node that belongs to a virtual LAN sends a request packet including a count value indicating the number of communication hops across nodes to each of its adjacent nodes that belong to the virtual LAN and are adjacent. Upon receiving the request packet, each of the adjacent nodes sends the request packet in which the count value is incremented or decremented to each of its adjacent nodes that belong to the virtual LAN and are adjacent to the node, excluding a sender of the request packet received, and sends a reply packet including the sender's address, an address of the node that is a replying node, and the count value to a given return destination. The return destination collects reply packets sent thereto and keeps track of the topology of the nodes constituting the virtual LAN from information contained in the reply packets.

摘要翻译： 属于虚拟LAN的任意节点将包含指示跨越节点的通信跳数的计数值的请求分组发送给属于虚拟LAN并且相邻的每个相邻节点。 在接收到请求分组时，每个相邻节点发送请求分组，其中计数值递增或递减到属于虚拟LAN的每个相邻节点，并且与节点相邻，不包括请求分组的发送者 接收并发送包括发送方地址，作为应答节点的节点的地址和计数值的应答分组到给定的返回目的地。 返回目的地收集发送到其中的应答分组，并且从包含在应答分组中的信息中跟踪构成虚拟LAN的节点的拓扑。