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公开(公告)号：US20200076512A1
公开(公告)日：2020-03-05
申请号：US16287796
申请日：2019-02-27
Applicant: Analog Devices Global Unlimited Company
Inventor： Laurence B. O'Sullivan , Shane Geary , Baoxing Chen , Bernard Patrick Stenson , Paul Lambkin , Patrick M. McGuinness , Stephen O'Brien , Patrick J. Murphy
Abstract: Isolators having a back-to-back configuration for providing electrical isolation between two circuits are described, in which multiple isolators formed on a single, monolithic substrate are connected in series to achieve a higher amount of electrical isolation for a single substrate than for isolators formed on separate substrates connected in series. Discrete dielectric regions positioned between isolator components forming an isolator provide electrical isolation between the isolator components as well as between the isolators formed on the substrate. The back-to-back isolator may provide one or more communication channels for transfer of information and/or power between different circuits.
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公开(公告)号：US10581423B1
公开(公告)日：2020-03-03
申请号：US16238338
申请日：2019-01-02
Applicant: Analog Devices Global Unlimited Company
Inventor： Srivatsan Parthasarathy , Sirui Luo , Thomas Paul Kearney , Yuanzhong Zhou , Donal Bourke , Jean-Jacques Hajjar
IPC: H01L27/02 , H02H9/00 , H03K17/081 , H03K17/0412
Abstract: Fault tolerant switches are provided herein. In certain embodiments, a fault tolerant switch includes a switch, a gate driver, and a clamp. The switch includes a switch p-type field effect transistor (PFET) and a switch n-type field effect transistor (NFET) electrically connected in series and controlled by the gate driver. Additionally, the clamp is electrically connected in parallel with the switch, and includes a forward protection circuit including a first diode and a first clamp FET in series, and a reverse protection circuit including a second diode and a second clamp FET in series. The clamp further includes a first gate bias circuit configured to bias a gate of the first clamp FET and a second gate bias circuit configured to bias a gate of the second clamp FET.
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公开(公告)号：US10551215B2
公开(公告)日：2020-02-04
申请号：US14737403
申请日：2015-06-11
Applicant: ANALOG DEVICES GLOBAL UNLIMITED COMPANY
Inventor： Eoin E. English , Javier Calpe Maravilla , Robert Guyol , Alan J. O'Donnell , Maria Jose Martinez , Jan Kubik , Krystian Balicki
IPC: G01D5/20
Abstract: An embodiment of a position sensing system includes a signal generation circuit to generate an excitation signal according to a selected characteristic signal, a drive circuit to drive an excitation source with the excitation signal, an input circuit to receive a sensor output while driving the excitation source, a signal detection circuit to identify a component of the sensor output corresponding to the characteristic signal, and a control circuit to determine the position of the movable object as a function of the identified component of the sensor output. The positioning system may be included an electronic camera, where the movable object may be a lens. The excitation source may be a conductive coil, the excitation a magnetic field, and the sensor a magneto resistive sensor. Alternatively, the excitation source may be an optical excitation source, the excitation an optical excitation, and the sensor an optical sensor.
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公开(公告)号：US10541721B2
公开(公告)日：2020-01-21
申请号：US15716197
申请日：2017-09-26
Applicant: Analog Devices Global Unlimited Company
Inventor： Michael W. O'Brien , Sudarshan Onkar
IPC: H03C3/09 , H04B10/556 , H04L27/12 , H04B1/7156 , H04L27/34 , H04L1/00 , H04L27/20 , H04J13/00
Abstract: Aspects of this disclosure relate to transmitting and/or receiving a frequency-shift keying signal including a packet that includes a preamble and a payload. The preamble has a first modulation index that has a smaller magnitude than a second modulation index of the payload. This can enhance frequency correction in a receive device that receives the packet.
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公开(公告)号：US20200021775A1
公开(公告)日：2020-01-16
申请号：US16174356
申请日：2018-10-30
Applicant: Analog Devices Global Unlimited Company
Inventor： Niall D. O'Connell , John CULLINANE , Isaac Molina Hernandez , Pablo Ventura , Alan M. BARRY
Abstract: Disclosed herein are systems and methods for communicating video signals and control data over a HD, wired, AC-coupled video and control link. In one aspect, an example system includes a scheduler that is configured to allocate time slots for exchange of data between a transmitter and a receiver over such a link. The scheduler is configured to, for each of at least one or more video lines of a video frame of a video signal acquired by a camera, allocate a plurality of time slots for transmitting a plurality of video components of said video line from the transmitter to the receiver, allocate one or more time slots for transmitting transmitter control data from the transmitter to the receiver, and allocate one or more time slots for transmitting receiver control data from the receiver to the transmitter.
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Patent Agency Ranking
公开(公告)号：US10528070B2
公开(公告)日：2020-01-07
申请号：US15969175
申请日：2018-05-02
Applicant: Analog Devices Global Unlimited Company
Inventor： Michael C. W. Coln , Michael Mueck , Quan Wan , Sandeep Monangi
Abstract: A low-noise, low-power reference voltage circuit can include an operational transconductance amplifier (OTA) with inputs coupled to a temperature-compensated voltage, such as can be provided by source-coupled first and second field-effect transistors (FETs) having different threshold voltages. A capacitive voltage divider can feed back a portion of a reference voltage output by the OTA to the inputs of the OTA to help establish or maintain the temperature-compensated voltage across the inputs of the OTA. A switching network can be used, such as initialize the capacitive voltage divider or other capacitive feedback circuit, such as during power-down cycles, or when resuming powered-on cycles. A switch can interrupt current to the OTA during the power-down cycles to save power. The cycled voltage reference circuit can provide a reference voltage to an ADC reservoir capacitor. Powering down can occur during analog input signal sampling, during successive approximation routine (SAR) conversion, or both.
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47.发明授权公开(公告)号：US10509426B2
公开(公告)日：2019-12-17
申请号：US15969204
申请日：2018-05-02
Applicant: Analog Devices Global Unlimited Company
Inventor： Sriram Ganesan , Amit Kumar Singh , Nilanjan Pal , Nitish Kuttan
IPC: G05F1/46 , G01R19/00 , G11C11/417
Abstract: Methods, systems and circuits for controlling the power available to the load, by reducing the power available to the load, and additionally or alternatively, limiting the current available by pre-establishing a maximum reference current. The reference current is compared to the actual or estimated current drawn by the load or part of the load. The comparison result is used to control a device or switch which disconnects the power supply or power supply regulator, whether connected directly to the load or connected via voltage dropping device, to one or more or a plurality of the load blocks when the maximum current is exceeded.
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公开(公告)号：US20190339337A1
公开(公告)日：2019-11-07
申请号：US16294192
申请日：2019-03-06
Applicant: Analog Devices Global Unlimited Company
Inventor： Yogesh Jayaraman SHARMA , Jochen SCHMITT , Paul R. BLANCHARD
Abstract: A calibration apparatus for calibrating a magnetic sensor configured to generate an output signal indicative of magnetic field strength when a bias signal is applied to it is disclosed. The apparatus includes a test magnetic field generator (MFG) to generate magnetic fields of known magnitude, and further includes a processor to control the MFG to generate a known magnetic field, control the sensor to generate a test output signal when the MFG generates the known magnetic field and a known bias signal is applied to the sensor, and determine how to change the bias signal based on a deviation of the measured test output signal from an expected output signal. Using a test MFG that produces known magnetic fields when known bias signals are applied to sensors allows evaluating and compensating for changes in sensitivity of the sensors by accordingly changing bias signals applied to the sensors.
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公开(公告)号：US10461635B1
公开(公告)日：2019-10-29
申请号：US15980342
申请日：2018-05-15
Applicant: Analog Devices Global Unlimited Company
Inventor： Jose Bernardo Din
Abstract: A charge pump circuit comprises a first charge transfer circuit path coupled including a first boost capacitor coupled to a first clock input, a first charge switch coupled to a circuit input, and a first discharge switch coupled to a circuit output; a second charge transfer circuit path including a second boost capacitor coupled to a second clock input, a second charge switch coupled to the circuit input, and a second discharge switch coupled to the circuit output; a first charge control circuit including a first gate switch coupled to a gate input of the first charge switch, and a first gate-drive capacitor coupled to the gate input of the second charge switch; and a second charge control circuit including a second gate switch coupled to a gate input of the second charge switch, and a second gate-drive capacitor coupled to the gate input of the first charge switch.
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公开(公告)号：US10445240B2
公开(公告)日：2019-10-15
申请号：US14450145
申请日：2014-08-01
Applicant: Analog Devices Global Unlimited Company
Inventor： Abhijit Giri , Saurbh Srivastava , Michael S. Allen
IPC: G06F12/0846
Abstract: Digital signal processors often operate on two operands per instruction, and it is desirable to retrieve both operands in one cycle. Some data caches connect to the processor over two busses and internally uses two or more memory banks to store cache lines. The allocation of cache lines to specific banks is based on the address that the cache line is associated. When two memory accesses map to the same memory bank, fetching the operands incurs extra latency because the accesses are serialized. An improved bank organization for providing conflict-free dual-data cache access—a bus-based data cache system having two data buses and two memory banks—is disclosed. Each memory bank works as a default memory bank for the corresponding data bus. As long as the two values of data being accessed belong to two separate data sets assigned to the two respective data buses, memory bank conflicts are avoided.
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