公开(公告)号：US20120250429A1

公开(公告)日：2012-10-04

申请号：US13435201

申请日：2012-03-30

Applicant: FRANCOIS TAILLIET ,  Marc Battista ,  Luc Wuidart

Inventor： FRANCOIS TAILLIET ,  Marc Battista ,  Luc Wuidart

IPC: G11C7/00 ,  H01L21/66 ,  H01L27/02

CPC classification number: H04W12/04 ,  G01R31/31719 ,  G06F21/70 ,  H01L22/14 ,  H01L22/20 ,  H01L2924/0002 ,  H04W12/08 ,  H01L2924/00

Abstract: A process is provided for fabricating a wafer including a plurality of chips separated by scribe lines. The method includes locking at least one chip on the wafer using a secret key, and writing the secret key into at least one memory present on the wafer.

Abstract translation: 提供了一种用于制造包括由划线分开的多个芯片的晶片的工艺。 该方法包括使用秘密密钥将晶片上的至少一个芯片锁定，并将秘密密钥写入存在于晶片上的至少一个存储器。

公开(公告)号：US08196005B2

公开(公告)日：2012-06-05

申请号：US12294714

申请日：2007-03-28

Applicant: Frank Kienle ,  Norbert Wehn ,  Torben Brack

Inventor： Frank Kienle ,  Norbert Wehn ,  Torben Brack

IPC: H03M13/00

CPC classification number: H03M13/3905 ,  H03M13/1165 ,  H03M13/1197 ,  H03M13/3972

Abstract: The method includes defining from all the check nodes at least one group of check nodes mutually connected through at least one second variable node defining an internal second variable node. The method includes performing for each group the joint updating of all the check nodes of the group via a Maximum-A-Posteriori (MAP) type process, and the updating of all the first variable nodes and all the second variable nodes connected to the group except the at least one internal second variable node. The method may include iteratively repeating the updates.

Abstract translation: 该方法包括从所有校验节点定义至少一组通过定义内部第二变量节点的至少一个第二变量节点相互连接的校验节点组。 该方法包括：通过最大后验（MAP）类型处理对每个组进行联合更新​​该组的所有校验节点，并且更新所有第一可变节点和连接到组的所有第二变量节点 除了至少一个内部第二变量节点。 该方法可以包括迭代地重复更新。

公开(公告)号：US08165549B2

公开(公告)日：2012-04-24

申请号：US12208921

申请日：2008-09-11

Applicant: Andras Pozsgay ,  Frédéric Paillardet

Inventor： Andras Pozsgay ,  Frédéric Paillardet

IPC: H04B1/06 ,  H03M1/66 ,  H04L27/00

CPC classification number: H03H17/025 ,  H03M3/504

Abstract: An electronic device, includes sigma-delta modulation circuit to operate with a clock signal and having output circuitry to deliver a digital data signal. First circuitry delivers a radiofrequency transposition signal. A notch filter includes radiofrequency digital-to-analog conversion blocks, having first input circuitry coupled to the output circuitry. Second input circuitry receives the radiofrequency transposition signal. Second output circuitry delivers a radiofrequency analog signal. Digital delay circuitry is controlled by the clock signal and includes a delay block between the two first input circuits. The frequency of a notch of the notch filter is related to the value of the delay from the delay block. Summation circuitry sums the radiofrequency signals.

Abstract translation: 电子设备包括用时钟信号操作并具有输出电路以输送数字数据信号的Σ-Δ调制电路。 第一个电路传送一个射频转置信号。 陷波滤波器包括射频数模转换块，其具有耦合到输出电路的第一输入电路。 第二输入电路接收射频转置信号。 第二输出电路提供射频模拟信号。 数字延迟电路由时钟信号控制，并且包括两个第一输入电路之间的延迟块。 陷波滤波器的陷波的频率与延迟块的延迟值有关。 求和电路对射频信号进行求和。

公开(公告)号：US08148748B2

公开(公告)日：2012-04-03

申请号：US12238308

申请日：2008-09-25

Applicant: Alexei Ankoudinov ,  Vladimir Rodov

Inventor： Alexei Ankoudinov ,  Vladimir Rodov

IPC: H01L29/66 ,  H01L29/74

CPC classification number: H01L29/861 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/7802

Abstract: An Adjustable Field Effect Rectifier uses aspects of MOSFET structure together with an adjustment pocket or region to result in a device that functions reliably and efficiently at high voltages without significant negative resistance, while also permitting fast recovery and operation at high frequency without large electromagnetic interference.

Abstract translation: 可调整场效应整流器使用MOSFET结构的一些方面以及调整口袋或区域，可以实现在高电压下可靠而高效地工作而无显着的负电阻的器件，同时还可以在高频下快速恢复和操作，而无需大的电磁干扰。

公开(公告)号：US08078804B2

公开(公告)日：2011-12-13

申请号：US11768462

申请日：2007-06-26

Applicant: Francesco Pappalardo ,  Giuseppe Notarangelo ,  Elena Salurso ,  Elio Guidetti

Inventor： Francesco Pappalardo ,  Giuseppe Notarangelo ,  Elena Salurso ,  Elio Guidetti

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F15/00 ,  G06F15/76 ,  G06F9/30 ,  G06F9/40

CPC classification number: G06F12/084 ,  G06F12/0886 ,  Y02D10/13

Abstract: A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for storing data for processing. The data locations are accessed either in a scalar mode or in a vectorial mode. This is done by explicitly mapping the data locations that are scalar and the data locations that are vectorial.

Abstract translation: 耦合到包括处理器集群的处理器的数据高速缓冲存储器适于通过在数据高速缓冲存储器中提供用于存储用于处理的数据的数据位置同时操作标量和矢量数据。 数据位置以标量模式或矢量模式进行访问。 这通过明确地映射标量的数据位置和矢量的数据位置来完成。

公开(公告)号：US20110051305A1

公开(公告)日：2011-03-03

申请号：US12773003

申请日：2010-05-03

Applicant: Alexei Ankoudinov ,  Vladimir Rodov ,  Richard A. Blanchard

Inventor： Alexei Ankoudinov ,  Vladimir Rodov ,  Richard A. Blanchard

IPC: H02H3/22

CPC classification number: H01L29/7815 ,  H01L27/088 ,  H01L29/423 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor protection devices, and related methods and systems, especially devices for providing series current limiting. The device typically comprises two regenerative building blocks and/or MOSFETs connected back-to-back in series, where one of the MOSFETs/Regenerative Building Blocks has an extra voltage probe electrode that provides a regenerative signal with self-limited voltage to the other via coupling to its gate electrode.

Abstract translation: 半导体保护装置及相关方法和系统，尤其是用于提供串联电流限制的装置。 器件通常包括串联背对背连接的两个再生建筑模块和/或MOSFET，其中一个MOSFET /再生构件模块具有一个额外的电压探针电极，其向另一个通孔提供具有自限制电压的再生信号 耦合到其栅电极。

公开(公告)号：US07899022B2

公开(公告)日：2011-03-01

申请号：US11220955

申请日：2005-09-07

Applicant: Armin Wellig ,  Julien Zory ,  Pasquale Imbesi

Inventor： Armin Wellig ,  Julien Zory ,  Pasquale Imbesi

IPC: H04B7/216

CPC classification number: H03M13/271 ,  H03M13/6566

Abstract: The block de-interleaving system includes an input for receiving a set of time-aligned blocks or interleaved data, physical memory unit, and a de-interleaving block for writing the blocks in the memory in a first predetermined manner and reading the blocks from the memory in a second predetermined manner to de-interleave the data of the blocks. The physical memory unit may include several different physical memories, and the de-interleaving block is adapted to completely write and read a block into and from one physical elementary memory.

Abstract translation: 块解交织系统包括用于接收一组时间对齐的块或交错数据的输入，物理存储器单元和用于以第一预定方式将块写入存储器的解交织块，并从块 存储器以第二预定方式对块的数据进行解交织。 物理存储器单元可以包括几个不同的物理存储器，并且去交织块适于完全地将一个块写入和读出一个物理基本存储器。

公开(公告)号：US07774674B2

公开(公告)日：2010-08-10

申请号：US11366167

申请日：2006-03-02

Applicant: Norbert Wehn ,  Frank Kienle ,  Torben Brack

Inventor： Norbert Wehn ,  Frank Kienle ,  Torben Brack

IPC: H03M13/00

CPC classification number: H03M13/1165 ,  H03M13/1137 ,  H03M13/635 ,  H03M13/6516 ,  H03M13/6566

Abstract: The LDPC decoder includes a processor for updating messages exchanged iteratively between variable nodes and check nodes of a bipartite graph of the LDPC code. The decoder architecture is a partly parallel architecture clocked by a clock signal. The processor includes P processing units. First variable nodes and check nodes are mapped on the P processing units according to two orthogonal directions. The decoder includes P main memory banks assigned to the P processing units for storing all the messages iteratively exchanged between the first variable nodes and the check nodes. Each main memory bank includes at least two single port memory partitions and one buffer the decoder also includes a shuffling network and a shift memory.

Abstract translation: LDPC解码器包括用于更新在LDPC码的二分图的可变节点和校验节点之间迭代交换的消息的处理器。 解码器架构是以时钟信号为时钟的部分并行架构。 处理器包括P处理单元。 第一个可变节点和校验节点根据两个正交方向映射在P个处理单元上。 解码器包括分配给P处理单元的P个主存储器组，用于存储在第一可变节点和校验节点之间迭代交换的所有消息。 每个主存储器包括至少两个单端口存储器分区和一个缓冲器。 解码器还包括洗牌网络和移位存储器。

公开(公告)号：US20090221318A1

公开(公告)日：2009-09-03

申请号：US12355899

申请日：2009-01-19

Applicant: Armin Wellig ,  Julien Zory

Inventor： Armin Wellig ,  Julien Zory

IPC: H04M1/00 ,  G06F11/00

CPC classification number: H03M13/6505 ,  H03M13/2703 ,  H03M13/2792 ,  H03M13/2796

Abstract: A method for de-interleaving S2 received sequences of interleaved received data samples respectively issued from S2 physical channels and to be associated with S1 output transport channels is provided. The S2 received sequences have been delivered, before transmission by a two-stage multi-interleaving device, from S1 initial sequences of ordered data samples respectively associated to S1 initial transport channels. The two-stage multi-interleaving device includes a first stage including S1 interleaving blocks respectively associated to the S1 initial transport channels, a second stage including S2 interleaving blocks respectively associated to the S2 physical channels, and an inter-stage of predetermined data-routing functions connected between the first and second stages.

Abstract translation: 提供了从S2物理信道分别发出并与S1输出传输信道相关联的用于去交织S2接收的交错接收数据样本序列的方法。 S2接收的序列在由两级多重交织装置发送之前已经从分别与S1个初始传输信道相关联的有序数据样本的S1个初始序列传送。 两级多交织装置包括：第一级，包括分别与S1初始传输信道相关联的S1交织块;第二级包括分别与S2物理信道相关联的S2交织块;以及预定数据路由 连接在第一和第二阶段之间的功能。

公开(公告)号：US07564832B2

公开(公告)日：2009-07-21

申请号：US10996121

申请日：2004-11-23

Applicant: Jorgen Van Parys

Inventor： Jorgen Van Parys

IPC: H04J3/06

CPC classification number: H04W74/04 ,  H04W74/06 ,  H04W84/18 ,  Y02D70/144 ,  Y02D70/25

Abstract: A Bluetooth master radio frequency unit addresses a slave radio frequency unit, to enable the slave to resynchronize to the master, by sending poll packets or null packets, the master being arranged to send sufficient null packets to enable the slave to resynchronize, before sending a poll packet, to determine whether the slave has resynchronized. This approach can provide the slave with the same number of synchronization packets as in the simpler algorithms, while allowing the slave to preserve more (transmit) power and still allowing the master to detect whether the slave has resynchronized or not (and thus to update a Link Supervision Timer for example). Notably this is also suitable for use in prescheduling implementations.

Abstract translation: 蓝牙主机射频单元寻址从射频单元，以使从机能够通过发送轮询分组或空分组重新同步主机，主机被安排为发送足够的空分组以使从机重新同步，然后发送 轮询数据包，以确定从站是否已重新同步。 这种方法可以为从属设备提供与简单算法相同数量的同步数据包，同时允许从器件保留更多（发送）功率，并且还允许主器件检测从器件是否已重新同步（从而更新 链路监控定时器）。 值得注意的是，这也适用于预先安排的实现。