公开(公告)号：US20220201697A1

公开(公告)日：2022-06-23

申请号：US17605204

申请日：2020-01-22

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tetsuya YAMAMOTO ,  Hidetoshi SUZUKI

IPC: H04W72/10 ,  H04W72/04

Abstract: The objective of the present invention is to implement appropriate radio communication processing in accordance with required criteria. This terminal is provided with: a control circuit which determines a method for determining a priority level of a first channel and a second channel having mutually overlapping resource allocations in the time domain, on the basis of a parameter relating to control information indicating the allocations of the first channel and the second channel respectively; and a communication circuit for transmitting or receiving a signal to or from at least one of the first channel and the second channel, on the basis of the priority level.

公开(公告)号：US20220201655A1

公开(公告)日：2022-06-23

申请号：US17603855

申请日：2020-03-18

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Yang KANG ,  Tien Ming Benjamin KOH ,  Lei HUANG ,  Chan Wah NG ,  Hong Cheng Michael SIM ,  Madhav GUPTA ,  Hidetoshi SUZUKI

IPC: H04W72/02 ,  H04W72/06 ,  H04W72/04 ,  H04W72/12

Abstract: The present disclosure provides communication apparatuses and communication methods for soft-segregation of resource pool for V2X communication apparatuses. The communication apparatuses include a communication apparatus which comprises circuitry, which, in operation, allocates a resource from a plurality of resources based on resource allocation information, the resource allocation information indicative of a likelihood of allocating the resource from the plurality of resources based on a transmission profile relating to a signal; and a transmitter, which, in operation, transmits the signal to a target communication apparatus using the allocated resource.

公开(公告)号：US20220201323A1

公开(公告)日：2022-06-23

申请号：US17476947

申请日：2021-09-16

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi KANOH ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Takashi HASHIMOTO

IPC: H04N19/513 ,  H04N19/159 ,  H04N19/186 ,  H04N19/182

Abstract: Provided is an encoder that achieves further improvement. The encoder includes processing circuitry and memory. Using the memory, the processing circuitry: obtains two prediction images from two reference pictures; derives a luminance gradient value of each pixel position in each of the two prediction images; derives a luminance local motion estimation value of each pixel position in a current block; generates a luminance final prediction image using a luminance value and the luminance gradient value in each of the two prediction images, and the luminance local motion estimation value of the current block; and generates a chrominance final prediction image using at least one of the luminance gradient value of each of the two prediction images or the luminance local motion estimation value of the current block, and chrominance of each of the two prediction images.

公开(公告)号：US20220201289A1

公开(公告)日：2022-06-23

申请号：US17693612

申请日：2022-03-14

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH

IPC: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/186

Abstract: An encoder includes memory and circuitry. The circuitry, using the memory, (i) selects a mode from among a plurality of modes each for deriving a motion vector, and derives a motion vector for a current block via the selected mode, and (ii) performs inter prediction encoding on the current block, using the derived motion vector, via one of a skip mode and a non-skip mode different from the skip mode. The plurality of modes include a plurality of first modes each for predicting the motion vector for the current block based on an encoded block neighboring the current block without encoding information indicating a motion vector into a stream. When a second mode included in the plurality of first modes is selected, the current block is encoded via the non-skip mode regardless of presence or absence of a residual coefficient.

公开(公告)号：US20220196892A1

公开(公告)日：2022-06-23

申请号：US17599640

申请日：2020-03-27

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tsuyoshi MORIYAMA ,  Kohei NOMA ,  Hideki AOYAMA ,  Mitsuaki OSHIMA

IPC: G02B5/02 ,  F21V8/00 ,  B05B7/16

Abstract: A light beam emission system includes: a blower that forms a flow path in which aerosol flows; and an emitter that emits a light beam. At least part of the light beam propagates along the flow path of the aerosol.

公开(公告)号：US11368819B2

公开(公告)日：2022-06-21

申请号：US16939443

申请日：2020-07-27

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Yutaka Murakami

IPC: H04W4/06 ,  H04B7/185 ,  H04W28/14 ,  H04W84/06 ,  H04W88/16

Abstract: A controller, which is a communication device, includes: a transfer unit including a function of transferring data received from a first terminal to another communication device via wireless communication; and a determination unit configured to determine whether first information is included in the data received by the transfer unit, the first information indicating that the data is to be multicast. The transfer unit is further configured to multicast the data to a second terminal when the determination unit determines that the first information is included in the data, the second terminal and the first terminal being different terminals.

公开(公告)号：US11368685B2

公开(公告)日：2022-06-21

申请号：US16942634

申请日：2020-07-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Chong Soon Lim ,  Ru Ling Liao ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Han Boon Teo ,  Jing Ya Li

IPC: H04N19/52 ,  H04N19/119 ,  H04N19/176

Abstract: Provided is an encoder which includes circuitry and memory. The circuitry encodes an image block using the memory. In encoding the image block, the circuitry: obtains one or more size parameters related to a size of the image block; determines whether the one or more size parameters and one or more thresholds satisfy a determined relationship; encodes a split parameter when the one or more size parameters and the one or more thresholds are determined to satisfy the determined relationship, the split parameter indicating whether the image block is to be split into a plurality of partitions including a non-rectangular partition; and encodes the image block after splitting the image block into the plurality of partitions when the split parameter indicates that the image block is to be split into the plurality of partitions.

公开(公告)号：US20220191517A1

公开(公告)日：2022-06-16

申请号：US17686698

申请日：2022-03-04

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Hideyuki OHGOSE ,  Kiyofumi ABE ,  Hiroshi ARAKAWA ,  Tatsuro JURI ,  Kazuhito KIMURA

IPC: H04N19/176 ,  H04N19/103 ,  H04N19/436 ,  H04N19/146

Abstract: A video image encoding device, in a first mode, variable-length-encodes a residual coefficient to generate a coefficient code string, outputs the coefficient code string and the header information in a state in which the header information is associated with the coefficient code string, in a second mode, directly uses a differential image as a coefficient code string without variable-length-encoding the differential image, and outputs the coefficient code string and the header information in a state in which the header information is associated with the coefficient code string.

公开(公告)号：US11363299B2

公开(公告)日：2022-06-14

申请号：US17116137

申请日：2020-12-09

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Che Wei Kuo ,  Chong Soon Lim ,  Chu Tong Wang ,  Han Boon Teo ,  Hai Wei Sun ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/66 ,  H04N19/122 ,  H04N19/176 ,  H04N19/103 ,  H04N19/96

Abstract: An encoder includes circuitry and memory connected to the circuitry, and the circuitry, in operation: determines, based on a width and a height of a block, whether or not to disable a prediction mode in which the block is split along a partitioning line defined by a distance and an angle and then prediction is performed; and encodes the block with the prediction mode disabled or not disabled according to a result of the determination on whether or not to disable the prediction mode. Here, the distance is the shortest distance between the center of the block and the partitioning line, and the angle is an angle representing a direction from the center of the block toward the partitioning line in the shortest distance. The circuitry determines to disable the prediction mode when (i) a width-to-height ratio is at least 8 or (ii) a height-to-width ratio is at least 8.

公开(公告)号：US20220182648A1

公开(公告)日：2022-06-09

申请号：US17678608

申请日：2022-02-23

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie DRUGEON ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/30 ,  H04N19/70

Abstract: An encoder includes memory and circuitry coupled to the memory. The circuitry is configured to: generate an encoded bitstream that includes a multi-layer structure; and store, in the encoded bitstream, a syntax element having a value indicating that a layer in the multi-layer structure to be output by a decoder is arbitrarily specified, the syntax element defining that at least one layer is to be output from among layers arbitrarily specifiable by the decoder.