公开(公告)号：US10451802B2

公开(公告)日：2019-10-22

申请号：US16374214

申请日：2019-04-03

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Charles Baudot

IPC: G02B6/125 ,  G02B6/122 ,  G02B6/136 ,  G02B6/12

Abstract: A photonic integrated device includes a first waveguide and a second waveguide. The first and second waveguides are mutually coupled at a junction region which includes a bulge region. The bulge region is defined two successive etching operations using two distinct etch masks, where the first etching operation is a partial etch and the second etching operation is a complete etch.

公开(公告)号：US20190288005A1

公开(公告)日：2019-09-19

申请号：US16288737

申请日：2019-02-28

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Hassan El Dirani ,  Pascal Fonteneau

IPC: H01L27/12 ,  H01L29/417 ,  H02M7/5387

Abstract: An inverter includes a semiconductor substrate. A Z2-FET switch is disposed at a first surface of the semiconductor substrate and a further switch is disposed at the first surface of the semiconductor substrate. The further switch and the Z2-FET switch have current paths coupled between a first reference terminal and a second reference terminal.

公开(公告)号：US20190285799A1

公开(公告)日：2019-09-19

申请号：US16295929

申请日：2019-03-07

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sylvain GUERBER ,  Charles BAUDOT

IPC: G02B6/122

Abstract: An optical waveguide is configured to propagate a light signal. Metal vias are arranged along and on either side of a portion of the optical waveguide. Additional metal vias are further arranged along and on either side of the optical waveguide both upstream and downstream of the portion of the optical waveguide. The metal vias and additional metal vias are oriented orthogonal to a same plane, the same plane being orthogonal to a transverse cross-section of the portion of the optical waveguide.

公开(公告)号：US20190280024A1

公开(公告)日：2019-09-12

申请号：US15916912

申请日：2018-03-09

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/146

Abstract: A semiconductor body of a first conductivity type and doped with a first doping level includes, at a front side surface thereof, a well of a second conductivity type and a region doped with the first conductivity type at a second doping level greater than the first doping level. An insulated vertical gate structure separates the region from the well. Buried iInsulated electrodes extend from the front side surface completely through the well and into a portion of the semiconductor body underneath the well. A conductive material portion of each buried insulated electrode is configured to receive a bias voltage and a conductive material portion of insulated vertical gate structure is configured to receive a gate voltage. The semiconductor body is delimited by a capacitive deep trench isolation that is biased at the same voltage as the buried insulated electrode.

公开(公告)号：US10401571B2

公开(公告)日：2019-09-03

申请号：US15971665

申请日：2018-05-04

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Patrick Le Maitre ,  Jean-Francois Carpentier

IPC: G02B6/28 ,  G02B6/12 ,  G02B6/125

Abstract: The disclosure relates to an optical splitter including two waveguides on either side of an axis. Each waveguide includes a first segment and a second segment that are closer to the axis than the rest of the waveguide. The first segments are optically coupled and the second segments are optically coupled. Each guide includes between the first and second segment, starting from the first segment, a first curved section including in succession a curvature the concavity of which is turned the side opposite the axis then a curvature the concavity of which is turned towards the axis, and starting from the second segment a second curved section including in succession a curvature the concavity of which is turned the side opposite the axis then a curvature the concavity of which is turned towards the axis. The first curved sections of the two waveguides are curved differently.

公开(公告)号：US20190267473A1

公开(公告)日：2019-08-29

申请号：US16407383

申请日：2019-05-09

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexis GAUTHIER ,  Guillaume C. RIBES

IPC: H01L29/66 ,  H01L29/78 ,  H01L49/00 ,  H01L29/12 ,  H01L21/28 ,  H01L21/02 ,  H01L29/423

Abstract: A vertical transistor includes two portions of a gate conductor that extend within a layer of insulator. An opening extending through the later of insulator includes source, channel and drain regions form by epitaxy operations. A thickness of the portions of the gate conductor decreases in the vicinity of the channel region.

公开(公告)号：US20190267335A1

公开(公告)日：2019-08-29

申请号：US16278313

申请日：2019-02-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Didier DUTARTRE

IPC: H01L23/66 ,  H01L29/06 ,  H01L21/762

Abstract: An integrated circuit includes a substrate having at least one first domain and at least one second domain that is different from the at least one first domain. A trap-rich region is provided in the substrate at the locations of the at least one second domain only. Locations of the at least one first domain do not include the trap-rich region.

公开(公告)号：US20190265519A1

公开(公告)日：2019-08-29

申请号：US16254798

申请日：2019-01-23

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Stephane Monfray ,  Frédéric Boeuf

IPC: G02F1/025

Abstract: A photonic device includes a first region having a first doping type, and a second region having a second doping type, where the first region and the second region contact to form a vertical PN junction. The first region includes a silicon germanium (SiGe) region having a gradual germanium concentration.

公开(公告)号：US20190250212A1

公开(公告)日：2019-08-15

申请号：US16249530

申请日：2019-01-16

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Patrick Le Maitre ,  Jean-Francois Carpentier

IPC: G01R31/317 ,  G02B6/12

CPC classification number: G01R31/31728 ,  G01M11/3145 ,  G02B6/12004 ,  G02B6/12011 ,  G02B6/12016 ,  G02B6/12019 ,  G02B6/12023 ,  G02B6/12033 ,  G02B6/2773 ,  G02B6/29332 ,  H01S5/0268

Abstract: The invention concerns an optoelectronic chip including a pair of optical inputs having a same bandwidth, and each being adapted to a different polarization, at least one photonic circuit to be tested, and an optical coupling device configured to couple the two inputs to the circuit to be tested.

公开(公告)号：US20190250124A1

公开(公告)日：2019-08-15

申请号：US16275051

申请日：2019-02-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Getenet Tesega AYELE ,  Stephane MONFRAY

IPC: G01N27/414 ,  H01L23/522 ,  H01L29/423 ,  H01L21/768 ,  G01N27/416

Abstract: A detection stage of an electronic detection device, for example a pH meter, includes an insulating region that receives an element to be analyzed. The insulating region is positioned on a sensing conductive region. A biasing stage includes an electrically conductive region which is capacitively coupled to the conductive region. The electrically conductive region is formed in an uppermost metallization level along with a further conductive region. That further conductive region is electrically connected to the sensing conductive region by a via passing through an insulating layer which insulates the electrically conductive region from the sensing conductive region.